Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.6.5.10.2. PIPE Interface

The GTS transceiver situated closest to the HPS, are specifically reserved for the USB 3.1 protocol as shown in the following figure. The USB 3.1 controller is implemented within the HPS SS while the PCS and PHY portions are implemented within the GTS transceiver. A static mux decides whether the 2nd or 3rd channel of the QUAD is used.

Figure 172. Pipe Interface
Note: In the Pipe Interface figure above, HPS SS stands for the hard processor system sub-system, and HSSI SS is the high-speed Serdes to sub-system.
  • This supports single transceiver channel with PMA data rate of 5 Gbps with input of 100 MHz reference clock (fixed).
  • The PCS function is provided by the PIPE PCS block within the GTS transceiver.
  • Optional AVMM I/F is provided which can be accessed through soft fabric for debugging purposes. PHY and PIPE PCS register spaces are accessible through this interface.

The following figure shows the optional AVMM I/F Access

Figure 173. Pipe Inteface with Optional AVMM I/F Access

The following table provides the signal descriptions.

Table 234.  PIPE Interface Signal Descriptions
Name Width Clock Domain Description
HSSI Interface
o_tx_serial_p/n 2 - Differential Transceiver Serial Output, TX
i_rx_serial_p/n 2 - Differential Transceiver Serial Input, RX
i_refclk_p/n 2 -

Dedicated Reference Clock Input

  • Supported Frequency: 100MHz
  • Used for TX PLL and CDR of the GTS transceiver
  • In Agilex™ 5, either the LOCAL RefClk in every QUAD or the regional RefClk from the regional network can be used
i_pma_cpu_clk 1 -

Flux Clock Input needed for Transceiver operation

You must instantiate a GTS reset sequencer Intel FPGA IP, then this signal must be connected to the o_pma_cu_clk output of the GTS reset sequencer.

Note: Refer to the "Implementing the GTS Reset Sequencer Intel FPGA IP" chapter in the GTS Transceiver PHY User Guide.
ZAVMM Interface
i_reconfig_usb_reset 1 Async Active High Reset for AVMM
i_reconfig_usb_clk 1 -

AVMM Clock

Supported frequency range is 100 M to 150 MHz

i_reconfig_usb_address 18 i_reconfig_clk 18-bit Address (word addressable)
i_reconfig_usb_byteenable 4 i_reconfig_clk Byte enable
i_reconfig_usb_read 1 i_reconfig_clk Read strobe
o_reconfig_usb_readdata 32 i_reconfig_clk 32-bit Read data
o_reconfig_usb_readdata_valid 1 i_reconfig_clk Read Data valid
i_reconfig_usb_write 1 i_reconfig_clk Write strobe
i_reconfig_usb_writedata 32 i_reconfig_clk 32-bit Write data
o_reconfig_usb_waitrequest 1 i_reconfig_clk Wait Request