Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.3.6.4.4.1. Operation in Generic Work Mode

In generic work mode, the command engine module is bypassed allowing to send low level commands directly to the mini controller unit. The mini controller then creates the commands that can be processed by the NAND Flash device. In this operation mode, the host software is responsible of performing the low level process that is normally done by the command engine. This operation mode is expected to be used only when CDMA and PIO modes are not sufficient.

In generic work mode, only command 0, command 2, and command 3 registers are used. Similarly to the other work modes, the operation is triggered when command 0 register gets written. In this operation mode, only the slave DMA interface is used for data transfer.

The following tables describe the command layout that applies for this work mode. The unused fields labeled as Reserved should be set to 0.

Command 0 (offset 0x0000) Description

Table 201.   Structure of Command 0 Register in Generic Work Mode
Bit Name Description
31:30 CT The 2'b11 value indicates the generic work mode.
29:27 Reserved Reserved
26:24 TRD_NUM This field selects destination thread number for command. Software can select any available thread. Commands can be issued in parallel to all threads.
23:21 Reserved Reserved
20 INT If this bit is set, then an interrupt should be issued after this operation is finished. The status of the triggered interrupt is reported in trdX_comp field in the trd_comp_intr_status (0x0138) register, where interrupt bit is selected by the thread number selected by the TRD_NUM field (one bit per thread).
19:0 Reserved Reserved

Command 2 (offset 0x0008) Description

Table 202.   Structure of Command 2 Register in Generic Work Mode
Bit Name Description
31:0 CMD_VAL_L This field store lower part of the mini controller command

Command 3 (offset 0x000c) Description

Table 203.   Structure of Command 3 Register in Generic Work Mode
Bit Name Description
31:0 CMD_VAL_H This field store higher part of the mini ontroller command

The CMD_VAL_H and CMD_VAL_L fields are concatenated into one 64-bit word. These registers define the command requested to the mini controller to send to the NAND Flash device. The following table describes the structure of the command.

Table 204.   Field Definitions of a Command in Generic Work Mode
Bit Name Description
63:11 Input

Additional input values required in command sequence. The possible values could be command values, address values or number of data bytes to transfer. The required input to each sequence is defined in the following table Description of Sequences Available in Generic Work Mode. Bits that are not defined in the sequence should be set to zero.

Bit 15 is common for all sequences. It is used as a chip enable hold indicator (ce_hold). When set to 1, the controller does not turn off the active chip enable signal at the end of the sequence. The active chip enable is turned off at the end of the sequence when ce_hold is set to 0 or when incoming sequence is targeted to different device (different CE).

ce_hold should only be used for volume assignment process. Some devices may require keeping the CE# low through the whole set feature sequence and ce_hold can also be used for this purpose. During normal operation, this bit should be turned off.

Some instructions with address phase define the field No_of_BYTES. This field indicates how many address bytes to send to the NAND Flash device.

Devices with lower number of row address cycles are supported:

No_of_BYTES = 0 - one address byte sent to the device

No_of_BYTES = 1 - two address byte sent to the device

No_of_BYTES = 2 - three address byte sent to the device

No_of_BYTES = 3 - four address byte sent to the device

No_of_BYTES = 4 - five address byte sent to the device

No_of_BYTES = 5 - six address byte sent to the device

10:8

Bank num

This field informs the mini controller on which memory device the sequence needs to be executed (NAND device chip select). Only one chip is supported by HPS.
7

jedec_supp

The bit informs the mini controller about which set of commands will be used in the sequence. Primary commands complaint with ONFI spec (‘0’ value) or secondary commands compliant with Jedec spec (‘1’). This bit is valid only for a few commands as shown in the following table Description of Sequences Available in Generic Work Mode. For commands that do not use this bit, this bit should be set to 0.
6

tWB active

This bit tells the mini controller if it must wait for tWB time after sending the last CMD/ADDR/DATA in the sequence. This is relevant for the sequences 0, 1, 2. For other sequences, set this bit to 0
5:0

Instruction Type

This field defines the type of instruction. The assigned corresponding values are described in the following table Description of Sequences Available in Generic Work Mode.

Commands like read status, read status enhanced, and read ID must be directly followed by the data transfer. The list of sequences available in the generic work mode is shown in the following table. The information required to create the command is provided for each one of the sequences supported.

Table 205.  Description of Sequences Available in Generic Work Mode
Instruction Name Instruction Type Input [63:11]
CMD Sequence 0 [23:16] CMD

Execute command sequence on the NAND Flash interface.

Figure 101. CMD Sequence

ADDR Sequence

1

[63:56] ADDR5

[55:48] ADDR4

[47:40] ADDR3

[39:32] ADDR2

[31:24] ADDR1

[23:16] ADDR0

[13:11] No_of_BYTES

Execute address sequence on the NF interface. Up to six bytes of address can be sent in one sequence, maximum value of No_of_BYTES is five (six address cycles).

Figure 102. ADDR Sequence
Data Sequence 2

[62] di_strip

[58:56] corr_cap

[55:40] last_sector_size

[39:32] sector_cnt

[31:16] sector_size

[14] erased_page_detect_enable

[13] scrambler_enable

[12] ecc_enable

[11] direction

Transfer the data over the NF interface. The controller transfers the number of sectors defined in sector_cnt field. First it transfers n-1 sector of size defined by sector_size field. Then the controller transfers a sector of a size defined by the last_sector_size. If the sector_cnt is one, then 1 sector of size defined with last_sector_size is transferred. If sector_cnt is 0 or last_sector_size is 0, then the data sequence is not triggered. If sector_cnt is greater than one and sector_size is 0, the data sequence is not triggered. Every sector starts with a new data word transferred from/to data FIFO.

The controller automatically aligns the number of data written to/read from the NAND Flash device depending on the work mode. In 8-bit SDR work mode, if param_extended_X_mode is set high, the number of data is aligned to the 8-bit. In 8-bit SDR work mode, if param_extended_X_mode is set low, the number of data is aligned to the 16-bit. In 16-bit SDR work mode, if param_extended_X_mode is set high the number of data is aligned to the 16-bit. In 16-bit SDR work mode, if param_extended_X_mode is set low, the number of data is aligned to the 32-bit. In DDR work mode the number of data is aligned to the 16-bit.

The controller can skip sending certain number of bytes during the transfer. This is, the controller starts sending dummy bytes to the NAND Flash device (bytes defined by marker field in the skip_bytes_conf register). The number of bytes is defined by the skip_bytes field in the skip_bytes_conf register. The controller sends dummy bytes starting from offset defined by the skip_bytes_offset field. The offset is counted from the beginning of the transferred data package. The controller does not take into account the column address when calculating offset. This feature is enabled when skip_byte field is not 0 and skip_bytes_offset is not 0.

  • di_strip: data integrity strip bytes. This is valid when data integrity is enabled. If di_strip is low the data integrity data is sent to the NAND Flash device. This bit should not be set if erased pages detection feature is enabled, because in read direction the controller adds the CRC data to the data stream and it masks the erased pages presence.
  • corr_cap: correction capability.
  • last_sector_size: number of data to transfer in the last sector. This value cannot be zero. last_ sector_size value cannot be lower than 4B when sector_cnt is higher than 1.
  • sector_cnt: defines the number of sectors to transfer within a single sequence. The overall number of data to transfer equals (sector_size *(sector_cnt-1) + last_sector_size).This value cannot be zero.
  • sector_size: number of data to transfer per each sector except the last one. If the sector_cnt is greater than one, then this value cannot be zero. When ECC engine is enable, the sector size values do not include the ECC bits added in the sector, but they need to be considered to determine if all data and ECC information fits in a page in the NAND Flash device. sector_size value cannot be lower than 4B.
  • erased_page_detect_enable: 1'b0 indicates erased page detection is disabled, 1'b1 indicates that erased page detection is enabled.
  • scrambler_enable: 1'b0 indicates that Scrambler is disabled,1'b1indicates Scrambler is enabled.
  • ecc_enable: 1'b0 indicates that ECC is disabled (only data transfer occurs), 1'b1 indicates that ECC is enabled (data and ECC data transfer occurs).
  • direction: 1'b0 indicates read from NAND Flash device, 1'b1 indicates write to NAND Flash device.
Figure 103. Data Sequence
Read Sequence 3

[63:56] ADDR5

[55:48] ADDR4

[47:40] ADDR3

[39:32] ADDR2

[31:24] ADDR1

[23:16] ADDR0

[13:11] No_of_BYTES

Execute <00><ADDR><30> command sequence +tWB. The allowed No_of_BYTES values are three to five (four to six address cycles).

Figure 104. Read Sequence

Write Sequence

4

[63:56] ADDR5

[55:48] ADDR4

[47:40] ADDR3

[39:32] ADDR2

[31:24] ADDR1

[23:16] ADDR0

[13:11] No_of_BYTES

Execute <80><ADDR> command sequence +tADL for jedec_supp = 1'b0 or <81><ADDR> +tADL for jedec_supp = 1'b1. The allowed No_of_BYTES values are three to five (four to six address cycles).

Figure 105. Write Sequence

Reset Sequence

5 N/A

Execute <FF> command sequence +tFEAT.

Figure 106. Reset Sequence

Erase Sequence

6

[47:40] ADDR3

[39:32] ADDR2

[31:24] ADDR1

[23:16] ADDR0

[13:11] No_of_BYTES

Execute <60><ADDR><d0> command sequence +tWB. The allowed No_of_BYTES values are one to three (two to four address cycles).

Figure 107. Erase Sequence

Read Status Sequence

7

[11] F2_enable

Execute <70> or <F1/F2> sequence +tWHR.

If jedec_supp = 1’b0, the mini controller sends 70h. If jedec_supp = 1'b1, the mini controller sends the secondary command code F1h or F2h. The field F2_enable distinguish the type of command. If F2_enable is 1'b0 then F1h command is sent to the device. If F2_enable is 1'b1 then F2h command is sent to the device. This command must be directly followed by the data transfer.

Figure 108. Read Status Sequence

Read Status Enhanced Sequence

8

[47:40] ADDR3

[39:32] ADDR2

[31:24] ADDR1

[23:16] ADDR0

[13:11] No_of_BYTES

Execute <78><ADDR> sequence +tWHR. The allowed No_of_BYTES values are one to three (two to four address cycles). This command must be directly followed by the data transfer.

Figure 109. Read Status Enhanced Sequence

Read Cache Random Sequence

9

[63:56] ADDR5

[55:48] ADDR4

[47:40] ADDR3

[39:32] ADDR2

[31:24] ADDR1

[23:16] ADDR0

[13:11] No_of_BYTES

Execute <00><ADDR><31> command sequence +tWB for jedec_supp = 1'b0 or <60><ADDR><3C> +tWB for jedec_supp = 1'b1. The allowed No_of_BYTES values are three to five (four to six address cycles).

Figure 110. Read Cache Random Sequence

Copyback Read Sequence

10

[63:56] ADDR5

[55:48] ADDR4

[47:40] ADDR3

[39:32] ADDR2

[31:24] ADDR1

[23:16] ADDR0

[13:11] No_of_BYTES

Execute <00><ADDR><35> command sequence +tWB for jedec_supp = 1'b0 or <60><ADDR><35> +tWB for jedec_supp = 1'b1. The allowed No_of_BYTES values are one, two, three, four and five (two, three, four, five and six address cycles) depending on the jedec_supp setting. If jedec_supp = 1'b0 the allowed No_of_BYTES values are three and four and if jedec_supp = 1'b1 the allowed No_of_BYTES values are one and two.

Figure 111. Copyback Read Sequence

Copyback Program Sequence

11

[63:56] ADDR5

[55:48] ADDR4

[47:40] ADDR3

[39:32] ADDR2

[31:24] ADDR1

[23:16] ADDR0

[13:11] No_of_BYTES

Execute <85><ADDR> command sequence + tADL. The allowed No_of_BYTES values are three to five (four to six address cycles).

Figure 112. Copyback Program Sequence

Change Read Column Sequence

12

[63:56] ADDR5

[55:48] ADDR4

[47:40] ADDR3

[39:32] ADDR2

[31:24] ADDR1

[23:16] ADDR0

[13:11] No_of_BYTES

Execute <05><2xADDR><E0> command sequence +tCCS for jedec_supp = 1'b0 or <05><ADDR><E0> command sequence +tCCS for jedec_supp = 1'b1. If the jedec_supp is zero the number of address cycles is fixed to two, otherwise the number of address cycles depends on the No_of_BYTES. In this last case the allowed No_of_BYTES values are three, four or five (four, five or six address cycles).

Figure 113. Change Read Column Sequence

Change Read ColumnEnhanced Sequence

13

[63:56] ADDR5

[55:48] ADDR4

[47:40] ADDR3

[39:32] ADDR2

[31:24] ADDR1

[23:16] ADDR0

[13:11] No_of_BYTES

Execute <06><ADDR><E0> command sequence +tCCS. The allowed No_of_BYTES values are three to five (four to six address cycles).

Figure 114. Change Read Column Enhanced Sequence

Change Read Column Jedec Sequence

14

[63:56] ADDR5

[55:48] ADDR4

[47:40] ADDR3

[39:32] ADDR2

[31:24] ADDR1

[23:16] ADDR0

[13:11] No_of_BYTES

Execute <00><ADDR><05><2xADDR><E0> command sequence +tCCS. The allowed No_of_BYTES values are three to five (four to six address cycles).

Figure 115. Change Read Column Jedec Sequence

Multi-plane Read Sequence

15

[55:48] ADDR4

[47:40] ADDR3

[39:32] ADDR2

[31:24] ADDR1

[23:16] ADDR0

[13:11] No_of_BYTES

Execute <00><ADDR><32> command sequence +tWB for jedec_supp = 1'b0 or <60><ADDR> for jedec_supp = 1'b1. The allowed No_of_BYTES values are one, two, three and four (two, three, four and five address cycles). If jedec_supp = 1'b0 the allowed No_of_BYTES values are three and four and if jedec_supp = 1'b1 the allowed No_of_BYTES values are one and two.

Figure 116. Multi-plane Read Sequence (jedec_supp=0)
Figure 117. Multi-plane Read Sequence (jedec_supp=1)

Multi-plane Block Erase Sequence

16

[47:40] ADDR3

[39:32] ADDR2

[31:24] ADDR1

[23:16] ADDR0

[13:11] No_of_BYTES

Execute <60><ADDR><D1> command sequence +tWB. The allowed No_of_BYTES values are one to three (two to four address cycles).

Figure 118. Multi-plane Block Erase Sequence

Multi-plane Block Erase Sequence ONFI®-Jedec

17

[63:56] ADDR5

[55:48] ADDR4

[47:40] ADDR3

[39:32] ADDR2

[31:24] ADDR1

[23:16] ADDR0

[13:11] No_of_BYTES

Execute <60><ADDR><60><ADDR><D0> command sequence +tWB. The allowed No_of_BYTES values are one and two (two and three address cycles). The controller sends consecutive address bytes in both address sequences. If two address bytes need to be sent in each address sequence controller sends ADDR0, ADDR1 in first sequence and ADDR2, ADDR3 in second sequence. For three address bytes case, the controller sends ADDR0, ADDR1, ADDR2 in the first address sequence and ADDR3, ADDR4, ADDR5 in the second address sequence.

Figure 119. Multi-plane Block Erase Sequence ONFI®-Jedec

Change Write Column Sequence

18

[31:24] ADDR1

[23:16] ADDR0

Execute <85> + tCWAW + <2xADDR> command sequence +tCCS.

Figure 120. Change Write Column Sequence

Change Row Address / Small Data Move Sequence

19

[63:56] ADDR5

[55:48] ADDR4

[47:40] ADDR3

[39:32] ADDR2

[31:24] ADDR1

[23:16] ADDR0

[13:11] No_of_BYTES

Execute <85><ADDR> command sequence +tCCS. The allowed No_of_BYTES values are three to five (four to six address cycles).

Figure 121. Change Row Address / Small Data Move Sequence

Synchronous Reset Sequence

20 N/A

Execute <FC> command sequence +tWB.

Figure 122. Synchronous Reset Sequence

Volume Select Sequence

21 [23:16] ADDR0

Execute <E1><1xADDR> command sequence +tVDLY.

Figure 123. Volume Select Sequence

ODT Configure Sequence

22

[31:24] ADDR1

[23:16] ADDR0

[13:11] No_of_BYTES

Execute <E2><ADDR> command sequence +tADL. The allowed No_of_BYTES values are zero and one (one and two address cycles).

Figure 124. ODT Configure Sequence

Set Features Sequence

23

[23:16] ADDR0

Execute <EF><1xADDR> command sequence +tADL. Some devices may have to keep the CE# low through the whole Set Feature sequence. ce_hold can be used for this purpose.

Figure 125. Set Features Sequence

Get Features Sequence

24

[23:16] ADDR0

Execute <EE><1xADDR> command sequence +tWB.

Figure 126. Get Features Sequence

LUN Get Features Sequence

25

[31:24] ADDR1

[23:16] ADDR0

Execute <D4><2xADDR> command sequence +tWB.

Figure 127. LUN Get Features Sequence

LUN Set Features Sequence

26

[31:24] ADDR1

[23:16] ADDR0

Execute <D5><2xADDR> command sequence +tADL.

Figure 128. LUN Set Features Sequence

Read ID Sequence

27

[23:16] ADDR0

Execute <90><1xADDR> command sequence +tWHR. This command must be directly followed by the data transfer.

Figure 129. Read ID Sequence

Read Parameter Page Sequence

28

[23:16] ADDR0

Execute <EC><1xADDR> command sequence +tWB.

Figure 130. Read Parameter Page Sequence

LUN Reset Sequence

31

[39:32] ADDR2

[31:24] ADDR1

[23:16] ADDR0

[13:11] No_of_BYTES

Execute <FA><ADDR> sequence +tWB. The allowed No_of_BYTES values are one and two (two and three address cycles).

Figure 131. LUN Reset Sequence