Visible to Intel only — GUID: sph1717145959379
Ixiasoft
1. Quick Start Guide
2. 10M/100M/1G Ethernet Design Example
3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example
5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example
7. Interface Signals Description
8. Configuration Registers Description
9. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
Visible to Intel only — GUID: sph1717145959379
Ixiasoft
1.5. Signal Tap Debugging
The IP provides a list of predefined debug signals to capture the behavior of the design example components.
To program the hardware design example on Agilex™ 5 devices:
- Click Tools > Signal Tap Logic Analyzer.
- Click Hardware Setup and select respective hardware for programming.
- Click on Scan Chain to select the proper JTAG.
- Click on the SOF Manager to browse and program the SOF.
- After the programming is complete, click any of the signals under the Setup window to view the signal behavior.
- In the Instance Manager toolbar, click Run Analysis. The signal capture and signal transitions is displayed in the Data window.
- Refer to the Signal Tap Logic Analyzer Introduction for more information about Signal Tap.
To start the signal tap debugging:
- Generate the design example for the Low Latency Ethernet 10G MAC IP.
- Open the .qpf file in the intel_eth_em10g32_0_EXAMPLE_DESIGN/LL10G_10G_*/ directory.
- In the Quartus® Prime Pro Edition software, click File > Open > <LL10G_*> > *.stp