Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 813665
Date 7/08/2024
Public
Document Table of Contents

1.5.1. Signal Tap Debug Signals

Table 4.  Signal Tap Debug Signals
Signal Description
Common Debug Signals for All Design Examples
o_src_rs_req Request signal to GTS Reset Sequencer.
i_src_rs_grant Grant signal from GTS Reset Sequencer.
o_tx_pll_locked Indicates that the TX serdes PLLs are locked.
o_rst_ack_n Active-low asynchronous acknowledgment signal for the i_rst_n reset.

Do not deassert the i_rst_n reset until the o_rst_ack_n asserts.

o_tx_rst_ack_n Active-low asynchronous acknowledgment signal for the i_tx_rst_n reset.

Do not deassert the i_tx_rst_n reset until o_tx_rst_ack_n asserts.

o_rx_rst_ack_n Active-low asynchronous acknowledgment signal for the i_rx_rst_n reset. Do not deassert the i_rx_rst_n reset until o_rx_rst_ack_n asserts.
operating_speed Indicates the current PHY speed set using the speed switch methodologies. This signal does not reflect the transceiver data rate.
  • 3’b000: 10G (Only valid for NBASE-T)
  • 3’b001: 1G
  • 3’b010: 100M
  • 3’b011: 10M
  • 3’b100: 2.5G
  • 3’b101: 5G (Only valid for NBASE-T)
  • 3’b110: Unused
  • 3’b111: Unused
Debug Signals for 10M/100M/1G and 2.5G Ethernet Design Example
i_system_pll_lock System PLL locked signal.
o_rx_is_lockedtoref Asynchronous output CDR lock status signal.
  • 1’b1 – CDR frequency is locked to the reference clock within the PPM threshold.
  • 1’b0 – CDR frequency is not locked to the reference clock within the PPM threshold.
led_link Asserted when the link is successful.
rx_is_lockedtodata Asserted when the CDR is locked to the RX data.
rx_ready Active high signal. When asserted, indicates that the RX datapath is ready to receive data.
tx_ready Active high signal. When asserted, indicates that the TX datapath is ready to transmit data.
xcvr_mode The current transceiver operating mode.
  • 2’b00: 1G
  • 2’b01: 2.5G
  • 2’b10: Reserved
  • 2’b11: Reserved
Debug Signals for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
o_cdr_lock This clock indicates that the recovered clocks are locked to data.
o_sys_pll_locked System PLL locked signal.
o_tx_lanes_stable Active-high asynchronous status signal for the TX datapath. Asserts when the TX datapath is ready to send data. Deasserts when the i_tx_rst_n or i_rst_n signal asserts.
o_rx_pcs_ready Active-high asynchronous status signal for the RX datapath. Asserts when the RX datapath is ready to receive data. Deasserts when the i_rx_rst_n or i_rst_n signal asserts.
rx_block_lock Asserted when the link synchronization for all speeds of USXGMII is successful.
channel_tx_ready Active high signal. When asserted, indicates that the RX datapath is ready to receive data.
channel_rx_ready Active high signal. When asserted, indicates that the RX datapath is ready to receive data.