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1. Quick Start Guide
2. 10M/100M/1G Ethernet Design Example
3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example
5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example
7. Interface Signals Description
8. Configuration Registers Description
9. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
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2.7.1. Packet Generator and Traffic Monitor Register Map
Byte Offset | R/W | Name | Description | HW Reset |
---|---|---|---|---|
0x00 | RW | NUMPKTS | The total number of Ethernet packets that the traffic generator generates and transmits to the design components. The width of this register is 32 bits. |
0 |
0x04 | RW | RANDOMLENGTH | Enables random packet length up to the value of the PKTLENGTH register.
|
0 |
0x08 | RW | RANDOMPAYLOAD | Enables random contents of the payload.
|
0 |
0x0C | RW | START | Start the generation of the Ethernet traffic by writing 0x01 to this register. | 0 |
0x10 | RW | STOP | Stops the generation of the Ethernet traffic by writing 0x01 to this register. | 0 |
0x14 | RW | MACSA0 | The lower 32 bits of the source address. | 0 |
0x18 | RW | MACSA1 | The upper 16 bits of the source address. The remaining 16 bits are not used. | 0 |
0x1C | RW | MACDA0 | The lower 32 bits of the destination address. | 0 |
0x20 | RW | MACDA1 | The upper 16 bits of the source address. The remaining 16 bits are not used. | 0 |
0x24 | RO | TXPKTCNT | The number of packets that the traffic generator transmitted. Read this register when the traffic generator is not active, for example, when the testing has completed. | 0 |
0x34 | RW | PKTLENGTH | When random-sized packets are enabled, this register specifies the maximum payload length. Otherwise, it specifies the length of the packet to be generated. The width of this register is 14 bits. |
0 |
Byte Offset | R/W | Name | Description | HW Reset |
---|---|---|---|---|
0x00 | RW | RXPKTCNT_EXPT | The number of packets that the traffic monitor expects to receive. | 0xFFFFFFFF |
0x04 | RO | RXPKTCNT_GOOD | The number of good packets received by the traffic monitor. | 0 |
0x08 | RO | RXPKTCNT_BAD | The number of packets received with CRC error. | 0 |
0x0C | RO | RXBYTECNT_LO32 | The lower 32 bits of the counter that keeps track of the total number of bytes the traffic monitor received. | 0 |
0x10 | RO | RXBYTECNT_HI32 | The upper 32 bits of the counter that keeps track of the total number of bytes the traffic monitor received. | 0 |
0x14 | RO | RXCYCLCNT_LO32 | The lower 32-bit of the counter that keeps track of the total number of clock cycles required by the traffic monitor to receive the expected number of packets. | 0 |
0x18 | RO | RXCYCLCNT_HI32 | The upper 32-bit of the counter that keeps track of the total number of clock cycles required by the traffic monitor to receive the expected number of packets. | 0 |
0x1C | RW | RXCTRL_STATUS | Monitors the configuration and status register.
|
0 |