Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 813665
Date 7/08/2024
Public
Document Table of Contents

2.3. Functional Description

The design example consists of various components. The following block diagram shows the design components and the top-level signals of the design example.

Figure 5. Block Diagram—10M/100M/1G Ethernet Design Example