Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813665
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10M/100M/1G Ethernet Design Example 3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature 4. 2.5G Ethernet Design Example 5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example 6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example 7. Interface Signals Description 8. Configuration Registers Description 9. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Signal Tap Debugging
1.2. Generating the Design x
1.2.1. Procedure 1.2.2. Design Example Parameters
1.3. Simulating the Design x
1.3.1. Procedure 1.3.2. Testbench
1.4. Compiling and Configuring the Design Example in Hardware x
1.4.1. Procedure 1.4.2. Hardware Setup
1.5. Signal Tap Debugging x
1.5.1. Signal Tap Debug Signals
2. 10M/100M/1G Ethernet Design Example x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals 2.7. Configuration Registers
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme 2.3.3. Reset Scheme
2.5. Hardware Testing x
2.5.1. Test Procedure
2.7. Configuration Registers x
2.7.1. Packet Generator and Traffic Monitor Register Map
3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Interface Signals 3.6. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme
3.4. Simulation x
3.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example x
4.1. Features 4.2. Hardware and Software Requirements 4.3. Functional Description 4.4. Simulation 4.5. Hardware Testing 4.6. Interface Signals 4.7. Configuration Registers
4.3. Functional Description x
4.3.1. Design Components 4.3.2. Clocking Scheme 4.3.3. Reset Scheme
4.5. Hardware Testing x
4.5.1. Test Procedure
4.7. Configuration Registers x
4.7.1. Packet Generator and Traffic Monitor Register Map
5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example x
5.1. Features 5.2. Hardware and Software Requirements 5.3. Functional Description 5.4. Simulation 5.5. Hardware Testing 5.6. Interface Signals 5.7. Configuration Registers
5.3. Functional Description x
5.3.1. Design Components 5.3.2. Clocking Scheme 5.3.3. Reset Scheme
5.5. Hardware Testing x
5.5.1. Test Procedure
5.7. Configuration Registers x
5.7.1. Packet Generator and Traffic Monitor Register Map
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example x
6.1. Features 6.2. Hardware and Software Requirements 6.3. Functional Description 6.4. Simulation 6.5. Interface Signals
6.3. Functional Description x
6.3.1. Design Components 6.3.2. Clocking Scheme 6.3.3. Reset Scheme
6.4. Simulation x
6.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
7. Interface Signals Description x
7.1. Clock and Reset Interface Signals 7.2. Avalon® Memory-Mapped Interface Signals 7.3. Avalon® Streaming Interface Signals 7.4. PHY Interface Signals 7.5. Status Interface 7.6. IEEE 1588v2 Timestamp Interface Signals
8. Configuration Registers Description x
8.1. Register Access Definition 8.2. Low Latency Ethernet 10G MAC 8.3. PHY
8.3. PHY x
8.3.1. 1G/2.5G/5G/10G Multirate PHY
1. Quick Start Guide
2. 10M/100M/1G Ethernet Design Example
3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example
5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example
7. Interface Signals Description
8. Configuration Registers Description
9. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

1.5.1. Signal Tap Debug Signals

Table 4.  Signal Tap Debug Signals
Signal Description
Common Debug Signals for All Design Examples
o_src_rs_req Request signal to GTS Reset Sequencer.
i_src_rs_grant Grant signal from GTS Reset Sequencer.
o_tx_pll_locked Indicates that the TX serdes PLLs are locked.
o_rst_ack_n Active-low asynchronous acknowledgment signal for the i_rst_n reset.

Do not deassert the i_rst_n reset until the o_rst_ack_n asserts.

o_tx_rst_ack_n Active-low asynchronous acknowledgment signal for the i_tx_rst_n reset.

Do not deassert the i_tx_rst_n reset until o_tx_rst_ack_n asserts.

o_rx_rst_ack_n Active-low asynchronous acknowledgment signal for the i_rx_rst_n reset. Do not deassert the i_rx_rst_n reset until o_rx_rst_ack_n asserts.
operating_speed Indicates the current PHY speed set using the speed switch methodologies. This signal does not reflect the transceiver data rate.
  • 3’b000: 10G (Only valid for NBASE-T)
  • 3’b001: 1G
  • 3’b010: 100M
  • 3’b011: 10M
  • 3’b100: 2.5G
  • 3’b101: 5G (Only valid for NBASE-T)
  • 3’b110: Unused
  • 3’b111: Unused
Debug Signals for 10M/100M/1G and 2.5G Ethernet Design Example
i_system_pll_lock System PLL locked signal.
o_rx_is_lockedtoref Asynchronous output CDR lock status signal.
  • 1’b1 – CDR frequency is locked to the reference clock within the PPM threshold.
  • 1’b0 – CDR frequency is not locked to the reference clock within the PPM threshold.
led_link Asserted when the link is successful.
rx_is_lockedtodata Asserted when the CDR is locked to the RX data.
rx_ready Active high signal. When asserted, indicates that the RX datapath is ready to receive data.
tx_ready Active high signal. When asserted, indicates that the TX datapath is ready to transmit data.
xcvr_mode The current transceiver operating mode.
  • 2’b00: 1G
  • 2’b01: 2.5G
  • 2’b10: Reserved
  • 2’b11: Reserved
Debug Signals for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
o_cdr_lock This clock indicates that the recovered clocks are locked to data.
o_sys_pll_locked System PLL locked signal.
o_tx_lanes_stable Active-high asynchronous status signal for the TX datapath. Asserts when the TX datapath is ready to send data. Deasserts when the i_tx_rst_n or i_rst_n signal asserts.
o_rx_pcs_ready Active-high asynchronous status signal for the RX datapath. Asserts when the RX datapath is ready to receive data. Deasserts when the i_rx_rst_n or i_rst_n signal asserts.
rx_block_lock Asserted when the link synchronization for all speeds of USXGMII is successful.
channel_tx_ready Active high signal. When asserted, indicates that the RX datapath is ready to receive data.
channel_rx_ready Active high signal. When asserted, indicates that the RX datapath is ready to receive data.
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