Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 813665
Date 7/08/2024
Public
Document Table of Contents

2.3.1. Design Components

Table 5.  Design Components
Component Description
LL 10GbE MAC

The Low Latency Ethernet 10G MAC Intel® FPGA IP with the following configuration:

  • Speed: 10M/100M/1G/2.5G
  • Datapath options: TX & RX
  • Enable ECC on memory blocks: Not selected
  • Enable preamble pass-through mode: Not selected
  • Enable priority-based flow control(PFC): Not selected
  • Enable supplementary address: Selected
  • Enable statistics collection: Selected
  • Statistics counters: Memory-based
  • TX and RX datapath Reset/Default To Enable: Selected
For the design example with the IEEE 1588v2 feature, the following additional parameters are configured:
  • Enable time stamping: Not selected
  • Enable PTP one-step clock support: Not selected
  • Enable asymmetry support: Not selected
  • Enable peer-to-peer support: Not selected
  • Timestamp fingerprint width: NA
  • Time Of Day format: NA
PHY The 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP with the following configuration:
  • Connect to MGBASE-T PHY: Selected
  • Connect to NBASE-T PHY: Not selected
  • Speed: 1G/2.5G
  • Enable SGMII bridge: Selected
  • Enabled IEEE 1588 Precision Time Protocol: Not selected
  • Enable GMII Adapter: Not selected
  • PHY ID (32 bit): 0x00000000
  • Default Mode: 1GbE
  • PMA Reference Frequency: 156.25 MHz
  • System PLL Frequency: 322.265625 MHz
GTS Reset Sequencer Resets the transceiver.
Address Decoder Decodes the addresses of the components.
System PLL Supports system PLL clocking mode for Direct PHY.