Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 813665
Date 7/08/2024
Public
Document Table of Contents

7.5. Status Interface

Table 27.  Status Interface Signals
Signal Direction Description

led_link

rx_block_lock

led_panel_link

Out Asserted when the link synchronization is successful.

led_an

Out Asserted when auto-negotiation is completed.

led_char_err

Out Asserted when a 10-bit character error is detected in the RX data.

led_disp_err

Out Asserted when a 10-bit running disparity error is detected in the RX data.

channel_tx_ready

channel_rx_ready

Out Asserted when the channel is ready for data transmission.
xgmii_rx_link_fault_status Out This signal indicates the status of the received data bytes. High indicates fault data bytes.
o_rst_ack_n Out Active-low asynchronous acknowledgement signal for the i_rst_n reset. Do not deassert i_rst_n reset until the o_rst_ack_n asserts.
o_tx_rst_ack_n Out Active-low asynchronous acknowledgement signal for the i_tx_rst_n reset. Do not deassert i_tx_rst_n reset until the o_tx_rst_ack_n asserts.
o_rx_rst_ack_n Out Active-low asynchronous acknowledgement signal for the i_rx_rst_n reset. Do not deassert i_rx_rst_n reset until the o_rx_rst_ack_n asserts.
o_tx_lanes_stable Out Active-high asynchronous status signal for the TX datapath. Asserts when the TX datapath is ready to send data. Deassert when i_tx_rst_n/i_rst_n signal asserts.
o_rx_pcs_ready Out Active-high asynchronous status signal for the RX datapath. Asserts when the RX datapath is ready to receive data. Deasserts when i_rx_rst_n/i_rst_n signal asserts.
rx_is_lockedtodata Out This signal indicates that the recovered clocks are locked to data.
o_tx_pll_locked Out Indicates TX serdes PLLs are locked. Do not use o_clk_tx_div until o_tx_pll_locked is high.