Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 813665
Date 7/08/2024
Public
Document Table of Contents

7.1. Clock and Reset Interface Signals

Table 23.  Clock and Reset Interface Signals
Signal Direction Width Description
csr_clk In 1 125 MHz configuration clock for the Avalon® memory-mapped interface and core logic.
i_tx_rst_n In 1

Active-low reset signal for the TX datapath.

i_rx_rst_n In 1

Active-low reset signal for the RX datapath.

mac_clk In 1 156.25 MHz configuration clock for the Avalon® streaming interface and 0 ppm frequency difference with refclk.

mac64b_clk

mac32b_clk

Out 1 156.25 MHz and 312.5 MHz configuration clock for the Avalon® streaming interface and 0 ppm frequency difference with refclk.

refclk_lg2p5g_p

In 1 156.25 MHz reference clock for PHY.
refclk_10g In 1 156.25 MHz reference clock for the System PLL.
rx_pma_clkout Out 1 CDR recovered clock.
reset 1 In 1 Assert this asynchronous and active-high signal to reset the whole design example.
reset In 1 Assert this asynchronous and active-high signal to reset the MAC and PHY soft IP datapath.
i_system_clk In 1 156.25 MHz reference clock for System PLL.
tx_digitalreset In [NUM_CHANNELS]

Asynchronous and active-high signal to reset MAC and PCS TX portion of the transceiver PHY.

rx_digitalreset In [NUM_CHANNELS]

Asynchronous and active-high signal to reset MAC and PCS RX portion of the transceiver PHY.

tx_digitalreset 1 Out [NUM_CHANNELS] Asynchronous and active-high signal to reset the MAC and PCS TX portion of of the transceiver PHY.
rx_digitalreset 1 Out [NUM_CHANNELS] Asynchronous and active-high signal to reset the MAC and PCS RX portion of of the transceiver PHY.
reconfig_reset In 1 Active-high reset signal for transceiver registers.
i_rst_n In 1 Active-low global reset asynchronous signal. Do not deassert until the o_rst_ack_n signal is asserted ('0').
i_rst_n 1 In 1 Active-low reset asynchronous signal.
mrphy_pll_clkout Out [NUM_CHANNELS] Output clock for 1G/2.5G/5G/10G Multirate Ethernet PHY IP. It provides 156.25 MHz timing reference for 2.5G, 62.5 MHz for 1G, 10M, and 100M.
1 Applicable for USXGMII Design Example.