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1. Quick Start Guide
2. 10M/100M/1G Ethernet Design Example
3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example
5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example
7. Interface Signals Description
8. Configuration Registers Description
9. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
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4.3.3. Reset Scheme
Upon power-up, reset the design example (i_rst_n, i_tx_rst_n, and i_rx_rst_n) and wait for o_rst_ack_n, o_tx_rst_ack_n, and o_rx_rst_ack_n signals to get asserted to de-assert the resets. Asserting these signals resets all channels and their components.
Figure 17. Reset Scheme for 2.5G Ethernet Design Example
An In-System Sources and Probes (ISSP) is instantiated to control the resets for the design.
Bit | ISSP |
---|---|
0 | i_rx_rst_n |
1 | i_tx_rst_n |
2 | i_rst_n |
3 | reconfig_reset |