Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 813665
Date 7/08/2024
Public
Document Table of Contents

3.3.1. Design Components

Table 10.  Design Components
Component Description
LL 10GbE MAC

The Low Latency Ethernet 10G MAC Intel® FPGA IP with the following configuration:

  • Speed: 1G/2.5G
  • Datapath options: TX & RX
  • Enable ECC on memory blocks: Not selected
  • Enable preamble pass-through mode: Not selected
  • Enable priority-based flow control (PFC): Not selected
  • Enable supplementary address: Selected
  • Enable statistics collection: Selected
  • Statistics counters: Memory-based
  • TX and RX datapath Reset/Default To Enable: Selected
  • Enable time stamping: Selected
  • Enable PTP one-step clock support: Selected
  • Enable asymmetry support: Not selected
  • Enable peer-to-peer support: Not selected
  • Timestamp fingerprint width: 4
  • Time of Day format: Enable both 96b and 64b Time of Day Format
PHY The 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP with the following configuration:
  • Connect to MGBASE-T PHY: Selected
  • Connect to NBASE-T PHY: Not selected
  • Speed: 1G/2.5G
  • Enable SGMII bridge: Not selected
  • Enabled IEEE 1588 Precision Time Protocol: Selected
  • Enable GMII Adapter: Not selected
  • PHY ID (32 bit): 0x00000000
  • Default Mode: 1 GbE
  • PMA Reference Frequency: 156.25 MHz
  • syspll_outclk_freq_mhz: 322.265 MHz
GTS Reset Sequencer Resets the transceiver.
Address Decoder Decodes the addresses of the components.
System PLL Supports system PLL clocking mode for Direct PHY.
Design Components for the IEEE 1588v2 Feature
Time of Day Clock The TOD for each channel.
TOD Synchronizer Synchronizes the master TOD to all local TODs.
Ethernet Packet Classifier Decodes the packet type of incoming PTP packets and returns the decoded information to the Low Latency Ethernet 10G MAC Intel® FPGA IP.