Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 813665
Date 7/08/2024
Public
Document Table of Contents

2.3.3. Reset Scheme

Upon power-up, reset the design example (i_rst_n, i_tx_rst_n, and i_rx_rst_n) and wait for o_rst_ack_n, o_tx_rst_ack_n, and o_rx_rst_ack_n signals to get asserted to de-assert the resets. Asserting these signals resets all channels and their components.

Figure 7. Reset Scheme for 10M/100M/1G Ethernet Design Example
An In-System Sources and Probes (ISSP) is instantiated to control the resets for the design.
Bit ISSP
0 i_rx_rst_n
1 i_tx_rst_n
2 i_rst_n
3 reconfig_reset