Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 813665
Date 7/08/2024
Public
Document Table of Contents

1.3.2. Testbench

Figure 4. Block Diagram of the Testbench
Table 3.  Testbench Components
Component Description
Device under test (DUT) The design example.
Avalon® driver Consists of Avalon® streaming master bus functional models (BFMs). This driver forms the TX and RX paths. The driver also provides access to the Avalon® memory-mapped interface of the DUT.
Ethernet packet monitors Monitor TX and RX datapaths, and display the frames in the simulator console.