Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 813665
Date 7/08/2024
Public
Document Table of Contents

7.2. Avalon® Memory-Mapped Interface Signals

Table 24.   Avalon® Memory-Mapped Interface Signals
Signal Direction Description

csr_mac_write

csr_phy_write

csr_mch_write

csr_dphy_rcfg_write

In Assert this signal to request a write to Avalon® memory-mapped address decoder.

csr_mac_read

csr_phy_read

csr_mch_read

csr_dphy_rcfg_read

In Assert this signal to request a read to Avalon® memory-mapped address decoder.

csr_mac_address

csr_phy_address

csr_mch_address

csr_dphy_rcfg_address

In Use this bus to specify the register address you want to read from or write to.

csr_mac_writedata

csr_phy_writedata

csr_mch_writedata

csr_dphy_rcfg_writedata

In Carries the data to be written to the specified register.

csr_mac_readdata

csr_phy_readdata

csr_mch_readdata

csr_dphy_rcfg_readdata

Out Carries the data read from the specified register.

csr_dphy_rcfg_raddatavalid

Out When asserted, this signal indicates that the read data is valid.

csr_mac_waitrequest

csr_phy_waitrequest

csr_mch_waitrequest

csr_dphy_rcfg_waitrequest

Out When asserted, this signal indicates that the IP is busy and not ready to accept any read or write requests.