Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 813665
Date 7/08/2024
Public
Document Table of Contents

1.1. Directory Structure

Figure 2. Directory Structure for the Design Example
Table 1.  Directory and File Description
Directory/File Description
altera_eth_top.qpf Quartus® Prime Pro Edition project file.
altera_eth_top.qsf Quartus® Prime Pro Edition settings file.
altera_eth_top.sv Design example top-level HDL.
altera_eth_top.sdc Synopsys Design Constraints (SDC) file.
rtl The folder that contains the design example synthesizable components.

rtl/altera_mge_rd.sv

rtl/altera_mge_channel.v

Design example DUT top-level files for the following Ethernet design examples:
  • 2.5G
  • 10M/100M/1G
rtl/alt_mge_reset_synchronizer.v Resets synchronizer file.

rtl/alt_mge_multi_channel.sv

rtl/alt_mge_channel.v

Design example DUT top-level files for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet design example.
rtl/<Design Component> The folder for each synthesizable component including Platform Designer generated IPs, such as LL 10GbE MAC, PHY, and FIFO.
simulation/ed_sim/models The folder that contains the testbench files.

simulation/ed_sim/cadence

simulation/ed_sim/mentor

simulation/ed_sim/synopsys/vcsmx

simulation/ed_sim/xcelium

The folder that contains the simulation script. It also serves as a working area for the simulator.

hwtesting/system_console_fm

hwtesting/system_console

The folder that contains system console scripts for hardware testing. All the required system console scripts are available in the folder system_console_fm. The folder system_console contains scripts that is only relevant to 2.5G and 10M/100M/1G .