Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 813665
Date 7/08/2024
Public
Document Table of Contents

7.4. PHY Interface Signals

Table 26.  PHY Interface Signals
Signal Direction Width Description

rx_serial_data

rx_serial_data_n

In

[NUM_CHANNELS][1]

RX serial input data

tx_serial_data

tx_serial_data_n

Out

[NUM_CHANNELS][1]

TX serial output data
xcvr_mode In [NUM_CHANNELS][2] Configures the transceiver operating mode.

2'b00: 1G

2'b01: 2.5G

xcvr_mode_out Out [NUM_CHANNELS][2] Outputs the current transceiver operating mode.

2'b00: 1G

2'b01: 2.5G

serial_i_rx_serial_data

serial_i_rx_serial_data

In [NUM_CHANNELS][1] RX serial input data.

serial_o_tx_serial_data

serial_o_tx_serial_data

Out [NUM_CHANNELS][1] TX serial output data.