Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 813665
Date 7/08/2024
Public
Document Table of Contents

5.5.1. Test Procedure

Follow these steps to test the design examples in hardware:

  1. Navigate to the hardware directory: <design_example>/LL10G_10G_USXGMII/hwtesting/system_console_fm.
  2. Click Tools > System Debugging Tools > System Console or run command: system-console &.
  3. Run the following command in the System Console:
    1. source main.tcl
    2. set_jtag <select_appropriate_jtag_master>
    Note: The set_jtag command places the Agilex™ 5 device on the JTAG chain.
  4. Run one of the following commands in the system console to start the test:
    1. If you want to trigger the test for a specific datarate and channel:

      TEST_EXT_LB <channel> <speed> <burst_size>

      Example: TEST_EXT_LB 0 10G 100000

      Note: You must connect the external loopback module QSFP28 to bank 1A before running the test.
      Table 18.  Command Parameters
      Parameter Valid Values Description
      channel 0, 1 The channel number to test.
      speed 10M, 100M, 1G, 2P5G, 5G, 10G The PHY speed.
      burst_size An integer value The number of packets to generate for the test.
    2. If you want to trigger the test for all the supported rates for both the channels:
      source hwtest_main.tcl
  5. The following sample output illustrate a successful hardware test run:
    Figure 23. Sample Test Output