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1. Quick Start Guide
2. 10M/100M/1G Ethernet Design Example
3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example
5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example
7. Interface Signals Description
8. Configuration Registers Description
9. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
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7.6. IEEE 1588v2 Timestamp Interface Signals
Signal | Direction | Width | Description |
---|---|---|---|
tx_egress_timestamp_96b_valid | Out | [NUM_CHANNELS] | When asserted, this signal qualifies the timestamp, tx_egress_timestamp_96b_data[], and the fingerprint, tx_egress_timestamp_96b_fingerprint[], of the TX frame. |
tx_egress_timestamp_96b_data | Out | [NUM_CHANNELS][96] | Carries the 96-bit egress timestamp in the following format:
|
tx_egress_timestamp_96b_fingerprint | Out | [NUM_CHANNELS][TSTAMP_FP_WIDTH] | Specifies the fingerprint of the TX frame that the 96-bit timestamp is for. |
tx_egress_timestamp_64b_valid | Out | [NUM_CHANNELS] | When asserted, this signal qualifies the timestamp, tx_egress_timestamp_64b_data[], and the fingerprint, tx_egress_timestamp_64b_fingerprint[], of the TX frame. |
tx_egress_timestamp_64b_data | Out | [NUM_CHANNELS][64] | Carries the 64-bit egress timestamp in the following format:
|
tx_egress_timestamp_64b_fingerprint | Out | [NUM_CHANNELS][TSTAMP_FP_WIDTH] | Specifies the fingerprint of the TX frame that the 64-bit timestamp is for. |
rx_egress_timestamp_96b_valid | Out | [NUM_CHANNELS] | When asserted, this signal qualifies the timestamp, rx_ingress_timestamp_96b_data[]. The MAC IP asserts this signal in the same clock cycle it asserts avalon_st_rx_startofpacket. |
rx_egress_timestamp_96b_data | Out | [NUM_CHANNELS][96] | Carries the 96-bit ingress timestamp in the following format:
|
rx_egress_timestamp_64b_valid | Out | [NUM_CHANNELS] | When asserted, this signal qualifies the timestamp, rx_ingress_timestamp_64b_data[]. The MAC IP asserts this signal in the same clock cycle it asserts avalon_st_rx_startofpacket. |
rx_egress_timestamp_64b_data | Out | [NUM_CHANNELS][64] | Carries the 64-bit ingress timestamp in the following format:
|