Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 813665
Date 7/08/2024
Public
Document Table of Contents

3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature

The 1G/2.5G Ethernet design example with the IEEE 1588v2 feature demonstrates an Ethernet solution for Agilex™ 5 devices using the Low Latency Ethernet 10G MAC Intel® FPGA IP operating at 1G and 2.5G.

Generate the design example from the Example Design tab of the Low Latency Ethernet 10G MAC Intel® FPGA IP parameter editor.