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Ixiasoft
1. Quick Start Guide
2. 10M/100M/1G Ethernet Design Example
3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example
5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example
7. Interface Signals Description
8. Configuration Registers Description
9. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
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Ixiasoft
3.1. Features
- Supports dual Ethernet channel operating at 1G and 2.5G using 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 devices.
- Supports IEEE 1588v2 feature.
- On the transmit and receive paths:
- Provides packet monitoring system.
- Reports Ethernet MAC statistics counter.