Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 813665
Date 7/08/2024
Public
Document Table of Contents

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 24.2
IP Version 2.1.0

The Low Latency 10G Ethernet (LL 10GbE) MAC Intel® FPGA IP for Agilex™ 5 devices provides the capability of generating design examples for selected configurations.

Figure 1. Development Stages for the Design Example
Note: Device support for Agilex™ 5 D-Series FPGAs and SoCs in the Quartus® Prime Pro Edition software version 24.2 is restricted. To enable D-Series device support in your instance of the Quartus® Prime Pro Edition software, contact your regional Altera sales representative.