Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813665
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10M/100M/1G Ethernet Design Example 3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature 4. 2.5G Ethernet Design Example 5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example 6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example 7. Interface Signals Description 8. Configuration Registers Description 9. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Signal Tap Debugging
1.2. Generating the Design x
1.2.1. Procedure 1.2.2. Design Example Parameters
1.3. Simulating the Design x
1.3.1. Procedure 1.3.2. Testbench
1.4. Compiling and Configuring the Design Example in Hardware x
1.4.1. Procedure 1.4.2. Hardware Setup
1.5. Signal Tap Debugging x
1.5.1. Signal Tap Debug Signals
2. 10M/100M/1G Ethernet Design Example x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals 2.7. Configuration Registers
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme 2.3.3. Reset Scheme
2.5. Hardware Testing x
2.5.1. Test Procedure
2.7. Configuration Registers x
2.7.1. Packet Generator and Traffic Monitor Register Map
3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Interface Signals 3.6. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme
3.4. Simulation x
3.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example x
4.1. Features 4.2. Hardware and Software Requirements 4.3. Functional Description 4.4. Simulation 4.5. Hardware Testing 4.6. Interface Signals 4.7. Configuration Registers
4.3. Functional Description x
4.3.1. Design Components 4.3.2. Clocking Scheme 4.3.3. Reset Scheme
4.5. Hardware Testing x
4.5.1. Test Procedure
4.7. Configuration Registers x
4.7.1. Packet Generator and Traffic Monitor Register Map
5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example x
5.1. Features 5.2. Hardware and Software Requirements 5.3. Functional Description 5.4. Simulation 5.5. Hardware Testing 5.6. Interface Signals 5.7. Configuration Registers
5.3. Functional Description x
5.3.1. Design Components 5.3.2. Clocking Scheme 5.3.3. Reset Scheme
5.5. Hardware Testing x
5.5.1. Test Procedure
5.7. Configuration Registers x
5.7.1. Packet Generator and Traffic Monitor Register Map
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example x
6.1. Features 6.2. Hardware and Software Requirements 6.3. Functional Description 6.4. Simulation 6.5. Interface Signals
6.3. Functional Description x
6.3.1. Design Components 6.3.2. Clocking Scheme 6.3.3. Reset Scheme
6.4. Simulation x
6.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
7. Interface Signals Description x
7.1. Clock and Reset Interface Signals 7.2. Avalon® Memory-Mapped Interface Signals 7.3. Avalon® Streaming Interface Signals 7.4. PHY Interface Signals 7.5. Status Interface 7.6. IEEE 1588v2 Timestamp Interface Signals
8. Configuration Registers Description x
8.1. Register Access Definition 8.2. Low Latency Ethernet 10G MAC 8.3. PHY
8.3. PHY x
8.3.1. 1G/2.5G/5G/10G Multirate PHY
1. Quick Start Guide
2. 10M/100M/1G Ethernet Design Example
3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example
5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example
7. Interface Signals Description
8. Configuration Registers Description
9. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

1.1. Directory Structure

Figure 2. Directory Structure for the Design Example
Table 1.  Directory and File Description
Directory/File Description
altera_eth_top.qpf Quartus® Prime Pro Edition project file.
altera_eth_top.qsf Quartus® Prime Pro Edition settings file.
altera_eth_top.sv Design example top-level HDL.
altera_eth_top.sdc Synopsys Design Constraints (SDC) file.
rtl The folder that contains the design example synthesizable components.

rtl/altera_mge_rd.sv

rtl/altera_mge_channel.v

Design example DUT top-level files for the following Ethernet design examples:
  • 2.5G
  • 10M/100M/1G
rtl/alt_mge_reset_synchronizer.v Resets synchronizer file.

rtl/alt_mge_multi_channel.sv

rtl/alt_mge_channel.v

Design example DUT top-level files for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet design example.
rtl/<Design Component> The folder for each synthesizable component including Platform Designer generated IPs, such as LL 10GbE MAC, PHY, and FIFO.
simulation/ed_sim/models The folder that contains the testbench files.

simulation/ed_sim/cadence

simulation/ed_sim/mentor

simulation/ed_sim/synopsys/vcsmx

simulation/ed_sim/xcelium

The folder that contains the simulation script. It also serves as a working area for the simulator.

hwtesting/system_console_fm

hwtesting/system_console

The folder that contains system console scripts for hardware testing. All the required system console scripts are available in the folder system_console_fm. The folder system_console contains scripts that is only relevant to 2.5G and 10M/100M/1G .
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