External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 7/08/2024
Public
Document Table of Contents

4.2.1. ref_clk for External Memory Interfaces (EMIF) IP

PLL reference clock input

Table 35.  Interface: ref_clkInterface type: clock
Port Name Direction Description
ref_clk input PLL reference clock input