External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

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ID 772538
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP 2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction 3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture 4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals 5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP 6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support 7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support 8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support 9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure 10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization 11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging 12. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
1.1. Release Information
2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction x
2.1. Agilex™ 7 M-Series EMIF IP Protocol and Feature Support 2.2. Agilex™ 7 M-Series EMIF IP Design Flow 2.3. Agilex™ 7 M-Series EMIF IP Design Checklist
3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture x
3.1. Agilex™ 7 M-Series EMIF Architecture: Introduction 3.2. Agilex™ 7 M-Series EMIF Sequencer 3.3. Agilex™ 7 M-Series EMIF Controller 3.4. Agilex™ 7 M-Series EMIF IP for Hard Processor Subsystem (HPS)
3.1. Agilex™ 7 M-Series EMIF Architecture: Introduction x
3.1.1. Agilex™ 7 M-Series EMIF Architecture: I/O Subsystem 3.1.2. Agilex™ 7 M-Series EMIF Architecture: I/O SSM 3.1.3. Agilex™ 7 M-Series EMIF Architecture: I/O Bank 3.1.4. Agilex™ 7 M-Series EMIF Architecture: I/O Lane 3.1.5. Agilex™ 7 M-Series EMIF Architecture: Input DQS Clock Tree 3.1.6. Agilex™ 7 M-Series EMIF Architecture: PHY Clock Tree 3.1.7. Agilex™ 7 M-Series EMIF Architecture: PLL Reference Clock Networks 3.1.8. Agilex™ 7 M-Series EMIF Architecture: Clock Phase Alignment 3.1.9. User Clock in Different Core Access Modes
3.1.3. Agilex™ 7 M-Series EMIF Architecture: I/O Bank x
3.1.3.1. Lockstep Configuration 3.1.3.2. DDR4 Pin Placement 3.1.3.3. DDR5 Pin Placement 3.1.3.4. LPDDR5 Pin Placement 3.1.3.5. I/O Sub-Bank Usage
3.2. Agilex™ 7 M-Series EMIF Sequencer x
3.2.1. Agilex™ 7 M-Series Mailbox Structure and Register Definitions
3.2.1. Agilex™ 7 M-Series Mailbox Structure and Register Definitions x
3.2.1.1. Mailbox Supported Commands 3.2.1.2. Mailbox Command Definitions
3.3. Agilex™ 7 M-Series EMIF Controller x
3.3.1. Hard Memory Controller
3.3.1. Hard Memory Controller x
3.3.1.1. Hard Memory Controller Features
4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals x
4.1. Agilex™ 7 M-Series EMIF IP Interfaces for DDR4 4.2. Agilex™ 7 M-Series EMIF IP Interfaces for DDR5 4.3. Agilex™ 7 M-Series EMIF IP Interfaces for LPDDR5 4.4. Agilex™ 7 M-Series EMIF IP Interfaces for Calibration Component
4.1. Agilex™ 7 M-Series EMIF IP Interfaces for DDR4 x
4.1.1. ref_clk for External Memory Interfaces (EMIF) IP 4.1.2. core_init_n for External Memory Interfaces (EMIF) IP 4.1.3. usr_async_clk for External Memory Interfaces (EMIF) IP 4.1.4. usr_clk for External Memory Interfaces (EMIF) IP 4.1.5. usr_rst_n for External Memory Interfaces (EMIF) IP 4.1.6. s0_axi4 for External Memory Interfaces (EMIF) IP 4.1.7. mem for External Memory Interfaces (EMIF) IP 4.1.8. oct for External Memory Interfaces (EMIF) IP
4.2. Agilex™ 7 M-Series EMIF IP Interfaces for DDR5 x
4.2.1. ref_clk for External Memory Interfaces (EMIF) IP 4.2.2. core_init_n for External Memory Interfaces (EMIF) IP 4.2.3. usr_async_clk for External Memory Interfaces (EMIF) IP 4.2.4. usr_clk for External Memory Interfaces (EMIF) IP 4.2.5. usr_rst_n for External Memory Interfaces (EMIF) IP 4.2.6. s0_axi4 for External Memory Interfaces (EMIF) IP 4.2.7. mem for External Memory Interfaces (EMIF) IP 4.2.8. i3c for External Memory Interfaces (EMIF) IP 4.2.9. mem_lbd for External Memory Interfaces (EMIF) IP 4.2.10. mem_lbs for External Memory Interfaces (EMIF) IP 4.2.11. oct for External Memory Interfaces (EMIF) IP
4.3. Agilex™ 7 M-Series EMIF IP Interfaces for LPDDR5 x
4.3.1. ref_clk for External Memory Interfaces (EMIF) IP 4.3.2. core_init_n for External Memory Interfaces (EMIF) IP 4.3.3. usr_async_clk for External Memory Interfaces (EMIF) IP 4.3.4. usr_clk for External Memory Interfaces (EMIF) IP 4.3.5. usr_rst_n for External Memory Interfaces (EMIF) IP 4.3.6. s0_axi4 for External Memory Interfaces (EMIF) IP 4.3.7. mem for External Memory Interfaces (EMIF) IP 4.3.8. oct for External Memory Interfaces (EMIF) IP
4.4. Agilex™ 7 M-Series EMIF IP Interfaces for Calibration Component x
4.4.1. s0_axi4lite_clk for External Memory Interface Calibration Component 4.4.2. s0_axi4lite_rst_n for External Memory Interface Calibration Component 4.4.3. s0_axil for External Memory Interface Calibration Component
5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example
6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support x
6.1. Agilex™ 7 M-Series FPGA EMIF IP Parameters for DDR4 6.2. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 6.3. DDR4 Board Design Guidelines
6.1. Agilex™ 7 M-Series FPGA EMIF IP Parameters for DDR4 x
6.1.1. Agilex™ 7 M-Series FPGA EMIF IP Parameter Descriptions for DDR4 6.1.2. Agilex™ 7 M-Series FPGA EMIF Memory Device IP Parameter Descriptions for DDR4 6.1.3. Agilex™ 7 M-Series FPGA EMIF Calibration IP Parameter Descriptions
6.2. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
6.2.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 6.2.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 6.2.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 6.2.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR4 EMIF IP
6.2.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
6.2.1.1. Estimating Pin Requirements 6.2.1.2. DIMM Options 6.2.1.3. Maximum Number of Interfaces
6.2.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
6.2.2.1. OCT 6.2.2.2. PLL
6.2.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR4 EMIF IP x
6.2.4.1. Address and Command Pin Placement for DDR4 6.2.4.2. DDR4 Data Width Mapping 6.2.4.3. General Guidelines - DDR4 6.2.4.4. x4 DIMM Implementation 6.2.4.5. Specific Pin Connection Requirements 6.2.4.6. Command and Address Signals 6.2.4.7. Clock Signals 6.2.4.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3. DDR4 Board Design Guidelines x
6.3.1. Terminations for DDR4 with Agilex™ 7 M-Series Devices 6.3.2. General Layout Routing Guidelines 6.3.3. Reference Stackup 6.3.4. Agilex™ 7 M-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies 6.3.5. DDR4 Routing Guidelines: Discrete (Component) Topologies
6.3.1. Terminations for DDR4 with Agilex™ 7 M-Series Devices x
6.3.1.1. Dynamic On-Chip Termination (OCT) 6.3.1.2. Dynamic On-Die Termination (ODT) in DDR4 6.3.1.3. Choosing Terminations on Agilex™ 7 M-Series FPGA Devices 6.3.1.4. On-Chip Termination Recommendations for Agilex™ 7 M-Series FPGA Devices
6.3.4. Agilex™ 7 M-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies x
6.3.4.1. One DIMM per Channel (1DPC) for UDIMM, RDIMM, and SODIMM DDR4 Topologies 6.3.4.2. Skew Matching Guidelines for DIMM Configurations 6.3.4.3. Power Delivery Recommendations for the Memory / DIMM Side
6.3.5. DDR4 Routing Guidelines: Discrete (Component) Topologies x
6.3.5.1. Single Rank x 8 Discrete (Component) Topology 6.3.5.2. Single Rank x 16 Discrete (Component) Topology 6.3.5.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and Single Rank x 16 Discrete (Component) Topologies 6.3.5.4. Skew Matching Guidelines for DDR4 Discrete Configurations 6.3.5.5. Power Delivery Recommendations for DDR4 Discrete Configurations 6.3.5.6. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines
6.3.5.6. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines x
6.3.5.6.1. DDR4 Byte Lane Swapping 6.3.5.6.2. DDR4 Address and Command and CLK Lane 6.3.5.6.3. DDR4 Interface x8 Data Lane 6.3.5.6.4. DDR4 Interface x4 Data Lane 6.3.5.6.5. Pin Swizzling
7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support x
7.1. Agilex™ 7 M-Series FPGA EMIF IP Parameters for DDR5 7.2. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 7.3. DDR5 Board Design Guidelines
7.1. Agilex™ 7 M-Series FPGA EMIF IP Parameters for DDR5 x
7.1.1. Agilex™ 7 M-Series FPGA EMIF IP Parameter Descriptions for DDR5 7.1.2. Agilex™ 7 M-Series FPGA EMIF Memory Device IP Parameter Descriptions for DDR5 7.1.3. Agilex™ 7 M-Series FPGA EMIF Calibration IP Parameter Descriptions
7.2. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
7.2.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 7.2.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 7.2.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 7.2.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR5 EMIF IP 7.2.5. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines
7.2.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
7.2.1.1. Estimating Pin Requirements 7.2.1.2. DIMM Options 7.2.1.3. Maximum Number of Interfaces
7.2.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
7.2.2.1. OCT 7.2.2.2. PLL
7.2.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP x
7.2.3.1. General Guidelines - DDR5 7.2.3.2. x4 DIMM Implementation 7.2.3.3. Specific Pin Connection Requirements 7.2.3.4. Command and Address Signals 7.2.3.5. Clock Signals 7.2.3.6. Data, Data Strobes, DM, and Optional ECC Signals
7.2.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR5 EMIF IP x
7.2.4.1. Address and Command Pin Placement for DDR5 7.2.4.2. DDR5 Data Width Mapping
7.2.5. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines x
7.2.5.1. DDR5 Byte Lane Swapping 7.2.5.2. DDR5 Address and Command and CLK Lane 7.2.5.3. DDR5 Interface x8 Data Lane 7.2.5.4. DDR5 Interface x4 Data Lane 7.2.5.5. Pin Swizzling
7.3. DDR5 Board Design Guidelines x
7.3.1. PCB Stack-up and Design Considerations 7.3.2. General Design Considerations 7.3.3. DDR Differential Signals Routing 7.3.4. Ground Plane and Return Path 7.3.5. RDIMM, UDIMM, and SODIMM Break-in Layout Guidelines 7.3.6. DRAM Break-in Layout Guidelines 7.3.7. DDR5 PCB Layout Guidelines 7.3.8. DDR5 Simulation Strategy
7.3.7. DDR5 PCB Layout Guidelines x
7.3.7.1. DDR5 Discrete Component/Memory Down Topology: up to 40-Bit Interface (1 Rank x8 or x16, 2 Rank x8 or x16) 7.3.7.2. Routing Guidelines for DDR5 Memory Down: 1 Rank or 2 Rank (x8 bit or x16 bit) Configurations 7.3.7.3. Routing Guidelines for DDR5 RDIMM, UDIMM, and SODIMM Configurations 7.3.7.4. Example of a DDR5 layout on an Altera FPGA Platform Board
8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support x
8.1. Agilex™ 7 M-Series FPGA EMIF IP Parameters for LPDDR5 8.2. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 8.3. LPDDR5 Board Design Guidelines
8.1. Agilex™ 7 M-Series FPGA EMIF IP Parameters for LPDDR5 x
8.1.1. Agilex™ 7 M-Series FPGA EMIF IP Parameter Descriptions for LPDDR5 8.1.2. Agilex™ 7 M-Series FPGA EMIF Memory Device IP Parameter Descriptions for LPDDR5 8.1.3. Agilex™ 7 M-Series FPGA EMIF Calibration IP Parameter Descriptions
8.2. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
8.2.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 8.2.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 8.2.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 8.2.4. Pin Placements for Agilex™ 7 M-Series FPGA LPDDR5 EMIF IP
8.2.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
8.2.1.1. Estimating Pin Requirements 8.2.1.2. DIMM Options 8.2.1.3. Maximum Number of Interfaces
8.2.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
8.2.2.1. OCT 8.2.2.2. PLL
8.2.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP x
8.2.3.1. General Guidelines - LPDDR5 8.2.3.2. Specific Pin Connection Requirements 8.2.3.3. Command and Address Signals 8.2.3.4. Clock Signals
8.2.4. Pin Placements for Agilex™ 7 M-Series FPGA LPDDR5 EMIF IP x
8.2.4.1. Address and Command Pin Placement for LPDDR5 8.2.4.2. LPDDR5 Data Width Mapping 8.2.4.3. LPDDR5 Byte Lane Swapping
8.3. LPDDR5 Board Design Guidelines x
8.3.1. PCB Stack-up and Design Considerations 8.3.2. General Design Considerations 8.3.3. DDR Differential Signals Routing 8.3.4. Ground Plane and Return Path 8.3.5. DRAM Break-in Layout Guidelines 8.3.6. LPDDR5 PCB Layout Guidelines 8.3.7. LPDDR5 Simulation Strategy
8.3.6. LPDDR5 PCB Layout Guidelines x
8.3.6.1. LPDDR5 Discrete Component/Memory Down Topology (1 Rank or 2 Rank, up to 64 Bit Interface) 8.3.6.2. Supported LPDDR5 Topologies 8.3.6.3. Example of an LPDDR5 Layout on an Altera® FPGA Platform Board
9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure x
9.1. Timing Closure 9.2. Optimizing Timing
9.1. Timing Closure x
9.1.1. Timing Analysis
9.1.1. Timing Analysis x
9.1.1.1. PHY or Core
10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization x
10.1. Interface Standard 10.2. Bank Management Efficiency 10.3. Data Transfer 10.4. Improving Controller Efficiency
10.4. Improving Controller Efficiency x
10.4.1. Frequency of Operation 10.4.2. Series of Reads or Writes 10.4.3. AXI to Memory Mapping
11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging x
11.1. Interface Configuration Performance Issues 11.2. Functional Issue Evaluation 11.3. Timing Issue Characteristics 11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 11.5. Debugging with the External Memory Interface Debug Toolkit 11.6. Generating Traffic with the Test Engine IP 11.7. Guidelines for Developing HDL for Traffic Generator 11.8. Guidelines for Traffic Generator Status Check
11.1. Interface Configuration Performance Issues x
11.1.1. Interface Configuration Bottleneck and Efficiency Issues
11.2. Functional Issue Evaluation x
11.2.1. Altera IP Memory Model 11.2.2. Vendor Memory Model 11.2.3. Transcript Window Messages
11.3. Timing Issue Characteristics x
11.3.1. Evaluating FPGA Timing Issues 11.3.2. Evaluating External Memory Interface Timing Issues
11.5. Debugging with the External Memory Interface Debug Toolkit x
11.5.1. Prerequisites for Using the EMIF Debug Toolkit 11.5.2. Configuring Your Design to Use the EMIF Debug Toolkit 11.5.3. Launching the EMIF Debug Toolkit 11.5.4. Using the EMIF Debug Toolkit
11.5.4. Using the EMIF Debug Toolkit x
11.5.4.1. Rerunning Calibration 11.5.4.2. Rerunning the Test Engine 11.5.4.3. Saving Debug Print 11.5.4.4. Calibration Reports 11.5.4.5. Driver Margining Tab 11.5.4.6. Pin Delay Settings Tab
11.8. Guidelines for Traffic Generator Status Check x
11.8.1. Status Check Using the Signal Tap Logic Analyzer 11.8.2. Exporting the Status Interface to the Top-Level Design
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP
2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction
3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture
4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals
5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP
6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support
7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support
8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support
9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure
10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization
11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging
12. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

8.1.1. Agilex™ 7 M-Series FPGA EMIF IP Parameter Descriptions for LPDDR5

The following topics describe the parameters available on each tab of the IP parameter editor, which you can use to configure your IP. Each parameter with an adjacent checkbox can be auto-computed. The checkbox to the left of the parameter controls whether its value is auto-computed (true) or set manually (false). If there is no checkbox to the left of a parameter, then it must be set manually.
Table 146.  Group: Example Design / Example Design
Display Name Description
HDL Selection

This option lets you choose the format of HDL in which generated simulation and synthesis files are created. You can select either Verilog or VHDL.

(Identifier: EX_DESIGN_HDL_FORMAT)
Synthesis

Generate Synthesis Example Design

(Identifier: EX_DESIGN_GEN_SYNTH)
Simulation

Generate Simulation Example Design

(Identifier: EX_DESIGN_GEN_SIM)
Core Clock Freq

Frequency of the core clock in MHz. This clock drives the traffic generator and NoC initiator (If in NoC mode)

Note: This parameter can be auto-computed.

(Identifier: EX_DESIGN_CORE_CLK_FREQ_MHZ)
Core Refclk Freq

PLL reference clock frequency in MHz for PLL supplying the core clock

(Identifier: EX_DESIGN_CORE_REFCLK_FREQ_MHZ)
NOC Refclk Freq

NOC Refclk Freq for the NOC control IP

Note: This parameter can be auto-computed.

(Identifier: EX_DESIGN_NOC_REFCLK_FREQ_MHZ)
Traffic Generator Remote Access

Specifies whether the Traffic Generator control and status registers are accessible via JTAG, exported to the fabric, or just disabled

(Identifier: EX_DESIGN_HYDRA_REMOTE)
Table 147.  Group: General IP Parameters / High-Level Parameters
Display Name Description
Technology Generation

Denotes the specific memory technology generation to be used

Note: This parameter can be auto-computed.

(Identifier: MEM_TECHNOLOGY)
Memory Format

Specifies the packaging format of the memory device

(Identifier: MEM_FORMAT)
Memory Device Topology

Topology used by memory device

(Identifier: MEM_TOPOLOGY)
Memory Ranks

Total number of physical ranks in the interface

(Identifier: MEM_NUM_RANKS)
Number of Channels

Number of channels

(Identifier: MEM_NUM_CHANNELS)
Device DQ Width

If the device is a DIMM: Specifies the full DQ width of the DIMM.

If the interface is composed of discrete components: Specifies the DQ width of each discrete component.

(Identifier: MEM_DEVICE_DQ_WIDTH)
Number of Components Per Rank

Number of components per rank

(Identifier: MEM_COMPS_PER_RANK)
Enable Frequency Set Point 1

Specifies whether or not a second Frequency Set Point will be used for FSP-enabled technologies

(Identifier: PHY_FSP1_EN)
Enable Frequency Set Point 2

Specifies whether or not a third Frequency Set Point will be used for FSP-enabled technologies

(Identifier: PHY_FSP2_EN)
ECC Mode

Specifies the type of ECC (if any) and the required number of side-band bits per channel that will be used by this EMIF instance. While not all required side-band bits necessarily carry ECC bits, all need to be connected to the memory device. If enabling ECC requires more side-band bits than necessary ECC bits, then ECC bits are transmitted on the least significant side-band bits.

Supported ECC types:

  • In-line – The controller uses one-eighth of the memory to store ECC data, the controller performs the ECC computation, and schedules additional writes/reads for ECC.
  • Link - ECC data is sent as part of the data burst, along side the usual strobe and data, using an otherwise unused pin (RDQS_t on writes, DMI on reads). This ECC type is supported only for 1600Mhz WCK frequency.

Note: This parameter can be auto-computed.

(Identifier: CTRL_ECC_MODE)
Total DQ Width

(Derived Parameter) This will be the width (in bits) of the mem_dq port on the memory interface.

For a component interface, it is calculated based on: (MEM_COMPS_PER_RANK * MEM_DEVICE_DQ_WIDTH + (8 bits if Side-band ECC is enabled, or 8 bits if AXI4 User Data is enabled in fabric modes, or 4 bits if AXI4 User Data is enabled in NoC mode)) * MEM_NUM_CHANNELS

For a DIMM-based interface, it is just MEM_DEVICE_DQ_WIDTH + (8 bits if side-band ECC is enabled, or 8 bits if AXI4 User Data is enabled in fabric modes, or 4 bits if AXI4 User Data is enabled in NoC mode) * MEM_NUM_CHANNELS.

(Identifier: MEM_TOTAL_DQ_WIDTH)
Memory Clock Frequency for Frequency Set Point 0

Specifies the FSP0 operating frequency of the memory interface in MHz. If you change the memory frequency, you should update the memory latency parameters on the Memory tab and the memory timing parameters on the Mem Timing tab.

Note: This parameter can be auto-computed.

(Identifier: PHY_MEMCLK_FSP0_FREQ_MHZ)
Memory Clock Frequency for Frequency Set Point 1

Specifies the FSP1 operating frequency of the memory interface in MHz. If you change the memory frequency, you should update the memory latency parameters on the Memory tab and the memory timing parameters on the Mem Timing tab.

Note: This parameter can be auto-computed.

(Identifier: PHY_MEMCLK_FSP1_FREQ_MHZ)
Memory Clock Frequency for Frequency Set Point 2

Specifies the FSP2 operating frequency of the memory interface in MHz. If you change the memory frequency, you should update the memory latency parameters on the Memory tab and the memory timing parameters on the Mem Timing tab.

Note: This parameter can be auto-computed.

(Identifier: PHY_MEMCLK_FSP2_FREQ_MHZ)
Instance ID

Instance ID of the EMIF IP. EMIF in the same bank, or connected to related user logic (e.g. to the same INIU), should have unique IDs in order to distinguish them when using the side-band interface. Valid values are 0-6.

(Identifier: INSTANCE_ID)
Table 148.  Group: General IP Parameters / Memory Device Preset Selection
Display Name Description
Use Memory Device Preset from file for FSP 0

Specifies whether MEM_PRESET_ID_FSP0 will be a value from Quartus (if false), or a value from a custom preset file path (if true)

(Identifier: MEM_PRESET_FILE_EN_FSP0)
Memory Preset custom file path for FSP 0

Path to a .qprs file on the users disk for Frequency Set Point 0

(Identifier: MEM_PRESET_FILE_QPRS_FSP0)
Use Memory Device Preset from file for FSP 1

Specifies whether MEM_PRESET_ID_FSP1 will be a value from Quartus (if false), or a value from a custom preset file path (if true)

(Identifier: MEM_PRESET_FILE_EN_FSP1)
Memory Preset custom file path for FSP 1

Path to a .qprs file on the users disk for Frequency Set Point 1, if enabled

(Identifier: MEM_PRESET_FILE_QPRS_FSP1)
Use Memory Device Preset from file for FSP 2

Specifies whether MEM_PRESET_ID_FSP2 will be a value from Quartus (if false), or a value from a custom preset file path (if true)

(Identifier: MEM_PRESET_FILE_EN_FSP2)
Memory Preset custom file path for FSP 2

Path to a .qprs file on the users disk for Frequency Set Point 2, if enabled

(Identifier: MEM_PRESET_FILE_QPRS_FSP2)
Memory Preset for FSP 0

The name of a preset that the user would like to load for LPDDR5 Frequency Set Point 0, describing the memory device that this EMIF will be targeting.

Note: This parameter can be auto-computed.

(Identifier: MEM_PRESET_ID_FSP0)
Memory Preset for FSP 1

The name of a preset that the user would like to load for LPDDR5 Frequency Set Point 1, describing the memory device that this EMIF will be targetting.

Note: This parameter can be auto-computed.

(Identifier: MEM_PRESET_ID_FSP1)
Memory Preset for FSP 2

The name of a preset that the user would like to load for LPDDR5 Frequency Set Point 2, describing the memory device that this EMIF will be targetting.

Note: This parameter can be auto-computed.

(Identifier: MEM_PRESET_ID_FSP2)
Table 149.  Group: General IP Parameters / Advanced Parameters / PHY / Topology
Display Name Description
Use NOC

Specifies whether we are using the NOC or bypassing it

Note: This parameter can be auto-computed.

(Identifier: PHY_NOC_EN)
Asynchronous Enable

Specifies whether the user logic is clocked based on the clock provided by the IP (Sync), or by a separate user clock (Async). If true - async mode is used, if false - sync mode is used.

(Identifier: PHY_ASYNC_EN)
AC Placement

Indicates location on the device where the interface will reside (specifically, the location of the AC lanes in terms IO BANK and TOP vs BOT part of the IO BANK). Legal ranges are derived from device floorplan. By default (value=AUTO), the most optimal location is selected (to maximize available frequency and data width).

Note: This parameter can be auto-computed.

(Identifier: PHY_AC_PLACEMENT)
PLL Reference Clock Frequency

Specifies what PLL reference clock frequency the user will supply. It is recommended to use the fastest possible PLL reference clock frequency because it leads to better jitter performance.

Note: This parameter can be auto-computed.

(Identifier: PHY_REFCLK_FREQ_MHZ)
Table 150.  Group: General IP Parameters / Advanced Parameters / FPGA I/O / FPGA I/O Settings
Display Name Description
Voltage

The voltage level for the I/O pins driving the signals between the memory device and the FPGA memory interface.

(Identifier: PHY_IO_VOLTAGE)
Table 151.  Group: General IP Parameters / Advanced Parameters / FPGA I/O / FPGA I/O Settings / Address/Command
Display Name Description
Drive Strength

This parameter allows you to change the output on chip termination settings for the selected I/O standard on the Address/Command Pins. Perform board simulation with IBIS models to determine the best settings for your design.

(Identifier: GRP_PHY_AC_X_R_S_AC_OUTPUT_OHM)
Table 152.  Group: General IP Parameters / Advanced Parameters / FPGA I/O / FPGA I/O Settings / Memory Clock
Display Name Description
Drive Strength

This parameter allows you to change the output on chip termination settings for the selected I/O standard on the CK Pins. Perform board simulation with IBIS models to determine the best settings for your design.

(Identifier: GRP_PHY_CLK_X_R_S_CK_OUTPUT_OHM)
Table 153.  Group: General IP Parameters / Advanced Parameters / FPGA I/O / FPGA I/O Settings / Data Bus
Display Name Description
I/O Standard

Specifies the I/O electrical standard for the data bus pins. The selected I/O standard configures the circuit within the I/O buffer to match the industry standard.

(Identifier: GRP_PHY_DATA_X_DQ_IO_STD_TYPE)
Drive Strength

This parameter allows you to change the output on chip termination settings for the selected I/O standard on the DQ Pins. Perform board simulation with IBIS models to determine the best settings for your design.

(Identifier: GRP_PHY_DATA_X_R_S_DQ_OUTPUT_OHM)
Slew Rate

Specifies the slew rate of the data bus pins. The slew rate (or edge rate) describes how quickly the signal can transition, measured in voltage per unit time. Perform board simulations to determine the slew rate that provides the best eye opening for the data bus signals.

(Identifier: GRP_PHY_DATA_X_DQ_SLEW_RATE)
Input Termination

This parameter allows you to change the input on chip termination settings for the selected I/O standard on the DQ Pins. Perform board simulation with IBIS models to determine the best settings for your design.

(Identifier: GRP_PHY_DATA_X_R_T_DQ_INPUT_OHM)
Initial Vrefin

Specifies the initial value for the reference voltage on the data pins(Vrefin). The specified value serves as a starting point and may be overridden by calibration to provide better timing margins.

(Identifier: GRP_PHY_DATA_X_DQ_VREF)
Table 154.  Group: General IP Parameters / Advanced Parameters / FPGA I/O / FPGA I/O Settings / PHY Inputs
Display Name Description
PLL Reference Clock Input Termination

This parameter allows you to change the input on chip termination settings for the selected I/O standard on the refclk input pins. Perform board simulation with IBIS models to determine the best settings for your design.

(Identifier: GRP_PHY_IN_X_R_T_REFCLK_INPUT_OHM)
Table 155.  Group: General IP Parameters / Advanced Parameters / FPGA I/O / FPGA I/O Settings / Decision Feedback Equilization (DFE)
Display Name Description
DFE Tap 1

This parameter allows you to select the amount of bias used on tap 1 of the FPGA DFE

(Identifier: GRP_PHY_DFE_X_TAP_1)
DFE Tap 2

This parameter allows you to select the amount of bias used on tap 2 of the FPGA DFE

(Identifier: GRP_PHY_DFE_X_TAP_2)
DFE Tap 3

This parameter allows you to select the amount of bias used on tap 3 of the FPGA DFE

(Identifier: GRP_PHY_DFE_X_TAP_3)
DFE Tap 4

This parameter allows you to select the amount of bias used on tap 4 of the FPGA DFE

(Identifier: GRP_PHY_DFE_X_TAP_4)
Table 156.  Group: General IP Parameters / Advanced Parameters / Mem I/O / Memory I/O Settings / Data Bus On-Die Termination (ODT)
Display Name Description
Target Write Termination

Specifies the target termination to be used during a write

(Identifier: GRP_MEM_ODT_DQ_X_TGT_WR)
Non-Target Termination

Specifies the termination to be used for the non-target rank in a multi-rank configuration

(Identifier: GRP_MEM_ODT_DQ_X_NON_TGT)
Idle Termination

Specifies the termination to be used for RTT_PARK and DQS_RTT_PARK. For power savings it is recommended to leave this as disabled.

(Identifier: GRP_MEM_ODT_DQ_X_IDLE)
Drive Strength

Specifies the termination to be used when driving read data from memory

(Identifier: GRP_MEM_ODT_DQ_X_RON)
Data Clock Termination

Specifies the termination to be used for the data clock (WCK)

(Identifier: GRP_MEM_ODT_DQ_X_WCK)
Table 157.  Group: General IP Parameters / Advanced Parameters / Mem I/O / Memory I/O Settings / Data Bus Reference Voltage (Vref)
Display Name Description
VrefDQ Value

Specifies the initial VrefDQ value to be used

(Identifier: GRP_MEM_DQ_VREF_X_VALUE)
Table 158.  Group: General IP Parameters / Advanced Parameters / Mem I/O / Memory I/O Settings / Address/Command Bus On-Die Termination (ODT)
Display Name Description
Common Termination

Common termination value that can be applied to CA/CK/CS for LPDDR4 and can be applied to CA/CK for LPDDR5

(Identifier: GRP_MEM_ODT_CA_X_CA_COMM)
CA Termination Enable

Enable the common termination value on the CA bus. For LPDDR4, enabling CA termination will have no effect unless the ODT_CA bond pad is HIGH.

(Identifier: GRP_MEM_ODT_CA_X_CA_ENABLE)
CS Termination Enable

Enable the common termination value on the CS bus for LPDDR4. For LPDDR5, this enables the fixed-value 80 Ohm (RZQ/3) CS termination if it is supported by the memory.

(Identifier: GRP_MEM_ODT_CA_X_CS_ENABLE)
CK Termination Enable

Enable the common termination value on the CK bus

(Identifier: GRP_MEM_ODT_CA_X_CK_ENABLE)
Table 159.  Group: General IP Parameters / Advanced Parameters / Mem I/O / Memory I/O Settings / Address/Command Bus Reference Voltage (Vref)
Display Name Description
VrefCA Value

Specifies the initial VrefCA value to be used

(Identifier: GRP_MEM_VREF_CA_X_CA_VALUE)
Table 160.  Group: General IP Parameters / Advanced Parameters / Mem I/O / Memory I/O Settings / Decision Feedback Equilization (DFE)
Display Name Description
DFE Tap 1

This parameter allows you to select the amount of bias used on tap 1 of the memory DFE

(Identifier: GRP_MEM_DFE_X_TAP_1)
Table 161.  Group: General IP Parameters / Advanced Parameters / AXI Settings / AXI Interface Settings
Display Name Description
Enable Debug Tools

If enabled, the AXI-L port will be connected to SLD nodes, allowing for a system-console avalon manager interface to interact with this AXI-L subordinate interface.

(Identifier: DEBUG_TOOLS_EN)
AXI-Lite Port Access Mode

Specifies whether the AXI-Lite port is connected to the fabric, the NOC, or disabled

Note: This parameter can be auto-computed.

(Identifier: AXI_SIDEBAND_ACCESS_MODE)
Table 162.  Group: General IP Parameters / Advanced Parameters / Additional Parameters / Additional String Parameters
Display Name Description
User Extra Parameters

Semi-colon seperated list of key/value pairs of extra parameters

(Identifier: USER_EXTRA_PARAMETERS)
Table 163.  Group: Example Design / Performance Monitor
Display Name Description
Enable performance monitoring

Enable performance monitor on all channels for measuring read/write transaction metrics

(Identifier: EX_DESIGN_PMON_ENABLED)
Table 164.  Group: Example Design / Traffic Generator Program
Display Name Description
Traffic Generator Program

Specifies the traffic pattern to be run.

(Identifier: EX_DESIGN_HYDRA_PROG)
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