External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 7/08/2024
Public
Document Table of Contents

7.2.5.4. DDR5 Interface x4 Data Lane

For DDR5 x4 interfaces, two nibbles must be packed into the same IO12 lane.

Four pins are reserved for DQS_T and DQS_C signals and the remaining eight pins implement the DQ signals. The IO12 lane is divided into upper and lower halves to accommodate each nibble. You cannot swap signals belonging to one nibble with signals belonging to the other nibble. DQ signals within a nibble swap group may be swapped with each other. You may also swap entire nibbles—that is, nibble 0 and nibble 1—with each other provided the DQS pin functionality transfers to the correct pin locations. However, this process is not recommended for JEDEC-compliant DIMM interfaces, as it prohibits the interoperability between DIMMs constructed with x4 components and DIMMs constructed with x8 components.

The following table lists the supported pin functionality in x4 mode and the pins that may be swapped with each other. Pins belonging to the same swap group may be freely interchanged with each other.

Table 139.  Pin Swapping Rules for DDR5 x4
Pin Index Within Byte Lane DDR5 x4 Data Lane Function Swap Consideration
0 DQ Pin (lower nibble) Swap group A Nibble 0
1 DQ Pin (lower nibble) Swap group A
2 DQ Pin (lower nibble) Swap group A
3 DQ Pin (lower nibble) Swap group A
4 DQS_T Pin (lower nibble) Fixed location (not swappable)
5 DQS_C Pin (lower nibble) Fixed location (not swappable)
6 DQS_T Pin (upper nibble) Fixed location (not swappable) Nibble 1
7 DQS_C Pin (upper nibble) Fixed location (not swappable)
8 DQ Pin (upper nibble) Swap group B
9 DQ Pin (upper nibble) Swap group B
10 DQ Pin (upper nibble) Swap group B
11 DQ Pin (upper nibble) Swap group B
  • Nibble 1 must correspond to DQS[17:9] on a physical JEDEC-compliant DIMM for x4/x8 interoperability.
  • Nibbles 0 and 1 must follow the same skew matching rules among all 12 signals in the IO12 lane as are specified for a x8-based DQS group.
Note:
  • Although the current version of the Quartus® Prime software may not enforce all of the rules listed in the above table, be aware that all of these rules may be enforced in later versions of the software.
  • At present, the Quartus® Prime software checks the following:
    • Address and command pin placement, per the table in the Address and Command Pin Placement for DDR5 topic, or the Agilex™ 7 External Memory Interface Pin Information file, which is available here: Pin-Out Files for Altera FPGA Devices.
    • For x8, the Quartus® Prime software checks the following:
      • DQS T/C are on pin index 4 and pin index 5 in a byte lane.
      • DM is on pin index 6.
      • DQ[x] are on pin indices [11:8] and [3:0].
    • For x4, the Quartus® Prime software checks the following:
      • DQS T/C on pin index 4 and pin index 5 and associated DQs are within the corresponding byte lane.
      • DQS T/C on pin index 6 and pin index 7 and associated DQs are within the corresponding byte lane.
      You are responsible for ensuring that these conditions are met.
  • The Quartus® Prime software does not currently check whether DQ pins associated with the lower nibble DQS are actually placed in pin[3:0] or whether DQ pins associated with the upper nibble DQS are actually placed in pin[11:8].