External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 7/08/2024
Public
Document Table of Contents

4.1.2. core_init_n for External Memory Interfaces (EMIF) IP

An input to indicate that core configuration is complete

Table 27.  Interface: core_init_nInterface type: reset
Port Name Direction Description
core_init_n input Core init signal going into EMIF. Used to generate the reset signal on the core-EMIF interface in fabric modes.