External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 12/04/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.3.4. usr_clk for EMIF

User clock interface

Table 50.  Interface: usr_clkInterface type: clock
Port Name Direction Description
usr_clk input User clock