External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 12/04/2023
Public

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7.2.5.5. Pin Swizzling

For information on pin swizzling, refer to Configuring DQ Pin Swizzling in the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Design Example User Guide.