Visible to Intel only — GUID: uaj1695226523566
Ixiasoft
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
2. Intel Agilex® 7 M-Series FPGA EMIF IP – Introduction
3. Intel Agilex® 7 M-Series FPGA EMIF IP – Product Architecture
4. Intel Agilex 7 M-Series FPGA EMIF IP – End-User Signals
5. Intel Agilex® 7 M-Series FPGA EMIF IP – Simulating Memory IP
6. Intel Agilex 7 M-Series FPGA EMIF IP – DDR4 Support
7. Intel Agilex® 7 M-Series FPGA EMIF IP – DDR5 Support
8. Intel Agilex 7 M-Series FPGA EMIF IP – LPDDR5 Support
9. Intel Agilex® 7 M-Series FPGA EMIF IP – Timing Closure
10. Intel Agilex® 7 M-Series FPGA EMIF IP – Controller Optimization
11. Intel Agilex® 7 M-Series FPGA EMIF IP – Debugging
12. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide
3.1.1. Intel Agilex® 7 M-Series EMIF Architecture: I/O Subsystem
3.1.2. Intel Agilex® 7 M-Series EMIF Architecture: I/O SSM
3.1.3. Intel Agilex® 7 M-Series EMIF Architecture: I/O Bank
3.1.4. Intel Agilex® 7 M-Series EMIF Architecture: I/O Lane
3.1.5. Intel Agilex® 7 M-Series EMIF Architecture: Input DQS Clock Tree
3.1.6. Intel Agilex® 7 M-Series EMIF Architecture: PHY Clock Tree
3.1.7. Intel Agilex® 7 M-Series EMIF Architecture: PLL Reference Clock Networks
3.1.8. Intel Agilex® 7 M-Series EMIF Architecture: Clock Phase Alignment
3.1.9. User Clock in Different Core Access Modes
6.2.4.1. Address and Command Pin Placement for DDR4
6.2.4.2. DDR4 Data Width Mapping
6.2.4.3. General Guidelines - DDR4
6.2.4.4. x4 DIMM Implementation
6.2.4.5. Specific Pin Connection Requirements
6.2.4.6. Command and Address Signals
6.2.4.7. Clock Signals
6.2.4.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3.5.1. Single Rank x 8 Discrete (Component) Topology
6.3.5.2. Single Rank x 16 Discrete (Component) Topology
6.3.5.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and Single Rank x 16 Discrete (Component) Topologies
6.3.5.4. Skew Matching Guidelines for DDR4 Discrete Configurations
6.3.5.5. Power Delivery Recommendations for DDR4 Discrete Configurations
6.3.5.6. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines
7.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins
7.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources
7.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP
7.2.4. Pin Placements for Intel Agilex 7 M-Series FPGA DDR5 EMIF IP
7.2.5. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines
7.3.1. PCB Stack-up and Design Considerations
7.3.2. General Design Considerations
7.3.3. DDR Differential Signals Routing
7.3.4. Ground Plane and Return Path
7.3.5. RDIMM, UDIMM, and SODIMM Break-in Layout Guidelines
7.3.6. DRAM Break-in Layout Guidelines
7.3.7. DDR5 PCB Layout Guidelines
7.3.8. DDR5 Simulation Strategy
7.3.7.1. DDR5 Discrete Component/Memory Down Topology: up to 40-Bit Interface (1 Rank x8 or x16, 2 Rank x8 or x16)
7.3.7.2. Routing Guidelines for DDR5 Memory Down: 1 Rank or 2 Rank (x8 bit or x16 bit) Configurations
7.3.7.3. Routing Guidelines for DDR5 RDIMM, UDIMM, and SODIMM Configurations
7.3.7.4. Example of a DDR5 layout on Intel FPGA Platform Board
11.1. Interface Configuration Performance Issues
11.2. Functional Issue Evaluation
11.3. Timing Issue Characteristics
11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer
11.5. Generating Traffic with the Test Engine IP
11.6. Guidelines for Developing HDL for Traffic Generator
11.7. Debugging with the External Memory Interface Debug Toolkit
Visible to Intel only — GUID: uaj1695226523566
Ixiasoft
4.2.6. s0_axi4 for EMIF
Fabric AXI interface to controller.
Port Name | Direction | Description |
---|---|---|
Write Address (Command) Channel | ||
s0_axi4_awaddr | input | Write address |
s0_axi4_awburst | input | Write burst type.
|
s0_axi4_awid | input | Write address ID |
s0_axi4_awlen | input | Write burst length. Any value between 0 and 255 is valid, representing a transfer of 1 to 256 beats. |
s0_axi4_awlock | input | Write lock type. This 2-bit signal is used to control exclusive accesses and locking.
|
s0_axi4_awqos | input | Write quality of service. Supported priority values range from 0 to 3, with 0 as the lowest priority. |
s0_axi4_awsize | input | Write burst size. AWSIZE = 5 (32 bytes) is supported by the memory controller when the AXI port is 256 bits, and only AWSIZE = 4 (16 bytes) is supported by the memory controller when the AXI port is 128 bits. |
s0_axi4_awvalid | input | Write address valid |
s0_axi4_awuser | input | Write address user signal.
|
s0_axi4_awprot | input | Write protection type. This 2-bit signal is used to control privileged and secure accesses.
|
s0_axi4_awready | output | Write address ready |
Write Data Channel | ||
s0_axi4_wdata | input | Write data |
s0_axi4_wlast | input | Write last. This signal indicates the last transfer in a write burst. |
s0_axi4_wready | output | Write ready. Indicates that the AXI port is ready to accept write data. |
s0_axi4_wstrb | input | Write strobes |
s0_axi4_wuser | input | Write user signal. Only applicable to the x40/x72 lockstep cases. The additional user bits to be written are sent on this interface. If a x36 interface is used, then only the lowest 32-bits are connected. |
s0_axi4_wvalid | input | Write valid |
Write Response Channel | ||
s0_axi4_bready | input | Response ready |
s0_axi4_bid | output | Write response ID |
s0_axi4_bresp | output | Write response. A response is sent for the entire burst.
|
s0_axi4_bvalid | output | Write response valid. |
Read Address (Command) Channel | ||
s0_axi4_araddr | input | Read address. |
s0_axi4_arburst | input | Read burst type.
|
s0_axi4_arid | input | Read write address ID |
s0_axi4_arlen | input | Read burst length. Any value between 0 and 128 255 is valid, representing a transfer of 1 to 256 beats. |
s0_axi4_arlock | input | Read lock type. This 2-bit signal is used to control exclusive accesses and locking.
|
s0_axi4_arqos | input | Read quality of service Supported priority values range from 0 to 3, with 0 as the lowest priority |
s0_axi4_arsize | input | Read burst size. AWSIZE = 5 (32 bytes) is supported by the memory controller when the AXI port is 256 bits, and only AWSIZE = 4 (16 bytes) is supported by the memory controller when the AXI port is 128 bits. |
s0_axi4_arvalid | input | Read address valid. |
s0_axi4_aruser | inout | Read address user signal.
|
s0_axi4_arprot | input | Read protection type. This 2-bit signal is used to control privileged ad secure accesses.
|
s0_axi4_arready | output | Read address ready |
Ready Data Channel | ||
s0_axi4_rdata | output | Read data |
s0_axi4_rid | output | Read ID |
s0_axi4_rlast | output | Read last. This signal indicates the last transfer in a read burst. |
s0_axi4_rready | input | Read ready |
s0_axi4_rresp | output | read response. A response is sent with each burst, indicating the status of that burst.
|
s0_axi4_ruser | output | Read user signal. Only applicable to the x40/x72 lockstep cases. These are the additional user bits received on this interface. If a x36 interface is used, then only the lowest 32-bits are connected. |
s0_axi4_rvalid | output | Read valid. |