Visible to Intel only — GUID: cjs1698967331243
Ixiasoft
Visible to Intel only — GUID: cjs1698967331243
Ixiasoft
7.1.2. Intel Agilex 7 FPGA EMIF Memory Device Description IP (DDR5) Parameter Descriptions
Display Name | Description |
---|---|
Configuration Filepath | Filepath to Save to (.qprs extension) (Identifier: MEM_CONFIG_FILE_QPRS) |
Display Name | Description |
---|---|
Memory Format | Specifies the packaging format of the memory device (Identifier: MEM_FORMAT) |
Enable Data Mask | Specifies whether byte masking is to be enabled by the memory. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_DM_EN) |
Density of Each Memory Component | Specifies the density of each memory component in Gbits. (Identifier: DDR5_MEM_DEVICE_DENSITY_GBITS) |
Display Name | Description |
---|---|
Device DQ Width | If the device is a DIMM: Specifies the full DQ width of the DIMM. If the interface is composed of discrete components: Specifies the DQ width of each discrete component. (Identifier: MEM_DEVICE_DQ_WIDTH) |
Memory Component Data Width | Specifies the data width of the memory component in bits. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_COMPONENT_DQ_WIDTH) |
Burst Length | Specifies the burst length of the memory interface. (Identifier: DDR5_MEM_DEVICE_BURST_LENGTH) |
Display Name | Description |
---|---|
Number of Ranks per DIMM | Number of ranks per DIMM Note: This parameter can be auto-computed. (Identifier: MEM_RANKS_PER_DIMM) |
Number of Channels Per DIMM | Number of channels per DIMM Note: This parameter can be auto-computed. (Identifier: MEM_CHANNELS_PER_DIMM) |
Device Bank Group Address Width | Specifies the width of the bank group address. (Identifier: DDR5_MEM_DEVICE_BANK_GROUP_ADDR_WIDTH) |
Device Bank Address Width | Specifies the width of the bank address. (Identifier: DDR5_MEM_DEVICE_BANK_ADDR_WIDTH) |
Device Row Address Width | Specifies the width of the row address. (Identifier: DDR5_MEM_DEVICE_ROW_ADDR_WIDTH) |
Device Column Address Width | Specifies the width of the column address. (Identifier: DDR5_MEM_DEVICE_COL_ADDR_WIDTH) |
Number of Differential Memory Clock Pairs | Specifies the width of clock interface according to the number of ranks. (Identifier: DDR5_MEM_DEVICE_CK_WIDTH) |
Display Name | Description |
---|---|
Memory Clock Frequency | Specifies the operating frequency of the memory interface in MHz. If you change the memory frequency, you must select a matching Preset from the dropdown (or create a custom one), to update all the timing parameters. Note: This parameter can be auto-computed. (Identifier: PHY_MEMCLK_FREQ_MHZ) |
Memory Speed Bin | Specifies the memory speed bin. (Identifier: DDR5_MEM_DEVICE_SPEEDBIN) |
Memory Read Latency | Specifies the read latency of the memory interface in cycles. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_CL_CYC) |
Memory Write Latency | Specifies the write latency of the memory interface in cycles. (Identifier: DDR5_MEM_DEVICE_CWL_CYC) |
Display Name | Description |
---|---|
tREFI1 | Specifies the maximum average refresh interval in normal refresh mode in nanoseconds. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TREFI1_NS) |
tREFI2 | Specifies the maximum average refresh interval in fine granularity refresh mode in nanoseconds. (Identifier: DDR5_MEM_DEVICE_TREFI2_NS) |
tREFISB | Specifies the maximum average refresh interval in fine granularity and same bank refresh mode in nanoseconds. (Identifier: DDR5_MEM_DEVICE_TREFISB_NS) |
tCCD_S | Specifies the CAS_n to CAS_n command delay for different bank group in cycles. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TCCD_S_CYC) |
tCCD_L | Specifies the CAS_n to CAS_n command delay for same bank group in cycles. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TCCD_L_CYC) |
tCCD_L_WR | Specifies the write CAS_n to write CAS_n command delay for same bank group in cycles. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TCCD_L_WR_CYC) |
tCCD_L_WR2 | Specifies the write CAS_n to write CAS_n command delay for same bank group and the second write is not RMW, in cycles. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TCCD_L_WR2_CYC) |
tRRD_S | Specifies the Activate-to-Activate command delay to different bank group for 1KB page size in cycles. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TRRD_S_CYC) |
tRRD_L | Specifies the Activate-to-Activate command delay to same bank group for 1KB page size in cycles. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TRRD_L_CYC) |
tFAW | Specifies the four activate window for 1KB page size in nanoseconds. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TFAW_NS) |
tRFC1 | Specifies the refresh operation delay in normal refresh mode in nanoseconds. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TRFC1_NS) |
tRFC2 | Specifies the refresh operation delay in fine granularity refresh mode in nanoseconds. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TRFC2_NS) |
tRFCSB | Specifies the refresh operation delay in fine granularity and same bank refresh mode in nanoseconds. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TRFCSB_NS) |
tRCD | Specifies the Activate-to-internal-Read-or-Write delay in nanoseconds. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TRCD_NS) |
tRP | Specifies the row precharge time in nanoseconds. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TRP_NS) |
tRAS | Specifies the Activate-to-Precharge command period in nanoseconds. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TRAS_NS) |
tRC (tRAS+tRP) | Specifies the Activate-to-Activate or Refresh command period in nanoseconds. (Identifier: DDR5_MEM_DEVICE_TRC_NS) |
tREFSBRD | Specifies the same bank refresh to activate delay in nanoseconds. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TREFSBRD_NS) |
tWR | Specifies the write recovery time in nanoseconds. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TWR_NS) |
tZQLAT | Specifies the ZQ calibration latch time in cycles. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TZQLAT_CYC) |
tZQCAL | Specifies the ZQ calibration time in nanoseconds. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TZQCAL_NS) |
tMRR | Specifies the Mode Register Read (MRR) command period in cycles. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TMRR_CYC) |
tMRR_P | Specifies the Mode Register Read (MRR) pattern to mode register read pattern command spacing in cycles. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TMRR_P_CYC) |
tMRW | Specifies the Mode Register Write (MRW) command period in cycles. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TMRW_CYC) |
tMRD | Specifies the Mode Register Set (MRS) command delay in cycles. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TMRD_CYC) |
tDFE | Specifies the Decision Feedback Equalization (DFE) Mode Register Write update delay time in nanoseconds. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TDFE_NS) |
tDLLK | Specifies the timing of DLLK in cycles. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TDLLK_CYC) |
tWTR_S | Specifies the delay from start of internal write transaction to internal read command for different bank group in nanoseconds. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TWTR_S_NS) |
tWTR_L | Specifies the delay from start of internal write transaction to internal read command for same bank group in nanoseconds. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TWTR_L_NS) |
tRTP | Specifies the internal read command to precharge command delay in cycles. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TRTP_CYC) |
tPPD | Specifies the Precharge-to-Precharge delay in cycles. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TPPD_CYC) |
tPD | Specifies the minimum power down time in cycles. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TPD_CYC) |
tACTPDEN | Specifies the timing of Activate command to power down entry command in cycles. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TACTPDEN_CYC) |
tPRPDEN | Specifies the timing of Precharge All Banks (PREab), Precharge Same Bank (PREsb), or Normal Precharge (PREpb) to power down entry command in cycles. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TPRPDEN_CYC) |
tREFPDEN | Specifies the timing of Refresh All Banks (REFab) or Refresh Same Bank (REFsb) command to power down entry command in cycles. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TREFPDEN_CYC) |
tXP | Specifies the exit power down to next valid command in cycles. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TXP_CYC) |
tCPDED | Specifies the command pass disable delay in cycles. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TCPDED_CYC) |
tCSL | Specifies the Self-Refresh CS_n low pulse width in nanoseconds. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TCSL_NS) |
tCKSRX | Specifies the valid clock requirement before SRX in cycles. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TCKSRX_CYC) |
tCSH_SREXIT | Specifies the self-refresh exit CS_n high pulse width in nanoseconds. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TCSH_SREXIT_NS) |
tDQSCK | Specifies the DQS_t, DQS_c rising edge output timing location from rising CK_t, CK_c in cycles. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TDQSCK_CYC) |
tWPRE_EN | Specifies the write preamble enable window in cycles. The window size depends on the write preamble mode. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TWPRE_EN_CYC) |
tDQSS | Specifies the host and system voltage/temperature drift window of first rising DQS_t preamble edge relative to CAS Write Latency (CWL) CK_t-CK_c edge in cycles. Note: This parameter can be auto-computed. (Identifier: DDR5_MEM_DEVICE_TDQSS_CYC) |