External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

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Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP 2. Intel Agilex® 7 M-Series FPGA EMIF IP – Introduction 3. Intel Agilex® 7 M-Series FPGA EMIF IP – Product Architecture 4. Intel Agilex 7 M-Series FPGA EMIF IP – End-User Signals 5. Intel Agilex® 7 M-Series FPGA EMIF IP – Simulating Memory IP 6. Intel Agilex 7 M-Series FPGA EMIF IP – DDR4 Support 7. Intel Agilex® 7 M-Series FPGA EMIF IP – DDR5 Support 8. Intel Agilex 7 M-Series FPGA EMIF IP – LPDDR5 Support 9. Intel Agilex® 7 M-Series FPGA EMIF IP – Timing Closure 10. Intel Agilex® 7 M-Series FPGA EMIF IP – Controller Optimization 11. Intel Agilex® 7 M-Series FPGA EMIF IP – Debugging 12. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP x
1.1. Release Information
2. Intel Agilex® 7 M-Series FPGA EMIF IP – Introduction x
2.1. Intel Agilex® 7 M-Series EMIF IP Protocol and Feature Support 2.2. Intel Agilex® 7 M-Series EMIF IP Design Flow 2.3. Intel Agilex® 7 M-Series EMIF IP Design Checklist
3. Intel Agilex® 7 M-Series FPGA EMIF IP – Product Architecture x
3.1. Intel Agilex® 7 M-Series EMIF Architecture: Introduction 3.2. Intel Agilex® 7 M-Series EMIF Sequencer 3.3. Intel Agilex® 7 M-Series EMIF Controller 3.4. Intel Agilex® 7 M-Series EMIF IP for Hard Processor Subsystem (HPS)
3.1. Intel Agilex® 7 M-Series EMIF Architecture: Introduction x
3.1.1. Intel Agilex® 7 M-Series EMIF Architecture: I/O Subsystem 3.1.2. Intel Agilex® 7 M-Series EMIF Architecture: I/O SSM 3.1.3. Intel Agilex® 7 M-Series EMIF Architecture: I/O Bank 3.1.4. Intel Agilex® 7 M-Series EMIF Architecture: I/O Lane 3.1.5. Intel Agilex® 7 M-Series EMIF Architecture: Input DQS Clock Tree 3.1.6. Intel Agilex® 7 M-Series EMIF Architecture: PHY Clock Tree 3.1.7. Intel Agilex® 7 M-Series EMIF Architecture: PLL Reference Clock Networks 3.1.8. Intel Agilex® 7 M-Series EMIF Architecture: Clock Phase Alignment 3.1.9. User Clock in Different Core Access Modes
3.1.3. Intel Agilex® 7 M-Series EMIF Architecture: I/O Bank x
3.1.3.1. Lockstep Configuration 3.1.3.2. DDR4 Pin Placement 3.1.3.3. DDR5 Pin Placement 3.1.3.4. LPDDR5 Pin Placement 3.1.3.5. I/O Sub-Bank Usage
3.2. Intel Agilex® 7 M-Series EMIF Sequencer x
3.2.1. Intel Agilex® 7 M-Series Mailbox Structure and Register Definitions
3.2.1. Intel Agilex® 7 M-Series Mailbox Structure and Register Definitions x
3.2.1.1. Mailbox Supported Commands 3.2.1.2. Mailbox Command Definitions
3.3. Intel Agilex® 7 M-Series EMIF Controller x
3.3.1. Hard Memory Controller
3.3.1. Hard Memory Controller x
3.3.1.1. Hard Memory Controller Features
4. Intel Agilex 7 M-Series FPGA EMIF IP – End-User Signals x
4.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interfaces for DDR4 4.2. Intel Agilex® 7 M-Series FPGA EMIF IP Interfaces for DDR5 4.3. Intel Agilex® 7 M-Series FPGA EMIF IP Interfaces for LPDDR5 4.4. Intel Agilex® 7 M-Series FPGA EMIF IP Interfaces for EMIF Calibration Component
4.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interfaces for DDR4 x
4.1.1. ref_clk for EMIF 4.1.2. core_init_n for EMIF 4.1.3. usr_async_clk for EMIF 4.1.4. usr_clk for EMIF 4.1.5. usr_rst_n for EMIF 4.1.6. s0_axi4 for EMIF 4.1.7. mem for EMIF 4.1.8. oct for EMIF
4.2. Intel Agilex® 7 M-Series FPGA EMIF IP Interfaces for DDR5 x
4.2.1. ref_clk for EMIF 4.2.2. core_init_n for EMIF 4.2.3. usr_async_clk for EMIF 4.2.4. usr_clk for EMIF 4.2.5. usr_rst_n for EMIF 4.2.6. s0_axi4 for EMIF 4.2.7. mem for EMIF 4.2.8. i3c for EMIF 4.2.9. mem_lbd for EMIF 4.2.10. mem_lbs for EMIF 4.2.11. oct for EMIF
4.3. Intel Agilex® 7 M-Series FPGA EMIF IP Interfaces for LPDDR5 x
4.3.1. ref_clk for EMIF 4.3.2. core_init_n for EMIF 4.3.3. usr_async_clk for EMIF 4.3.4. usr_clk for EMIF 4.3.5. usr_rst_n for EMIF 4.3.6. s0_axi4 for EMIF 4.3.7. mem for EMIF 4.3.8. oct for EMIF
4.4. Intel Agilex® 7 M-Series FPGA EMIF IP Interfaces for EMIF Calibration Component x
4.4.1. s0_axi4lite_clk for EMIF 4.4.2. s0_axi4lite_rst_n for EMIF 4.4.3. s0_axi4lite for EMIF
5. Intel Agilex® 7 M-Series FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example
6. Intel Agilex 7 M-Series FPGA EMIF IP – DDR4 Support x
6.1. Intel Agilex 7 M-Series FPGA EMIF IP Parameters for DDR4 6.2. Intel Agilex® 7 M-Series FPGA EMIF IP Pin and Resource Planning 6.3. DDR4 Board Design Guidelines
6.1. Intel Agilex 7 M-Series FPGA EMIF IP Parameters for DDR4 x
6.1.1. Intel Agilex® 7 FPGA EMIF IP Parameter for DDR4 6.1.2. Intel Agilex 7 FPGA EMIF Memory Device Description IP (DDR4) Parameter Descriptions 6.1.3. Intel Agilex 7 FPGA EMIF Calibration IP Parameter Descriptions
6.2. Intel Agilex® 7 M-Series FPGA EMIF IP Pin and Resource Planning x
6.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins 6.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources 6.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP 6.2.4. Pin Placements for Intel Agilex® 7 M-Series FPGA DDR4 EMIF IP
6.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins x
6.2.1.1. Estimating Pin Requirements 6.2.1.2. DIMM Options 6.2.1.3. Maximum Number of Interfaces
6.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources x
6.2.2.1. OCT 6.2.2.2. PLL
6.2.4. Pin Placements for Intel Agilex® 7 M-Series FPGA DDR4 EMIF IP x
6.2.4.1. Address and Command Pin Placement for DDR4 6.2.4.2. DDR4 Data Width Mapping 6.2.4.3. General Guidelines - DDR4 6.2.4.4. x4 DIMM Implementation 6.2.4.5. Specific Pin Connection Requirements 6.2.4.6. Command and Address Signals 6.2.4.7. Clock Signals 6.2.4.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3. DDR4 Board Design Guidelines x
6.3.1. Terminations for DDR4 with Intel Agilex® 7 M-Series Devices 6.3.2. General Layout Routing Guidelines 6.3.3. Reference Stackup 6.3.4. Intel Agilex® 7 M-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies 6.3.5. DDR4 Routing Guidelines: Discrete (Component) Topologies
6.3.1. Terminations for DDR4 with Intel Agilex® 7 M-Series Devices x
6.3.1.1. Dynamic On-Chip Termination (OCT) 6.3.1.2. Dynamic On-Die Termination (ODT) in DDR4 6.3.1.3. Choosing Terminations on Intel Agilex® 7 M-Series FPGA Devices 6.3.1.4. On-Chip Termination Recommendations for Intel Agilex® 7 M-Series FPGA Devices
6.3.4. Intel Agilex® 7 M-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies x
6.3.4.1. One DIMM per Channel (1DPC) for UDIMM, RDIMM, and SODIMM DDR4 Topologies 6.3.4.2. Skew Matching Guidelines for DIMM Configurations 6.3.4.3. Power Delivery Recommendations for the Memory / DIMM Side
6.3.5. DDR4 Routing Guidelines: Discrete (Component) Topologies x
6.3.5.1. Single Rank x 8 Discrete (Component) Topology 6.3.5.2. Single Rank x 16 Discrete (Component) Topology 6.3.5.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and Single Rank x 16 Discrete (Component) Topologies 6.3.5.4. Skew Matching Guidelines for DDR4 Discrete Configurations 6.3.5.5. Power Delivery Recommendations for DDR4 Discrete Configurations 6.3.5.6. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines
6.3.5.6. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines x
6.3.5.6.1. DDR4 Byte Lane Swapping 6.3.5.6.2. DDR4 Address and Command and CLK Lane 6.3.5.6.3. DDR4 Interface x8 Data Lane 6.3.5.6.4. DDR4 Interface x4 Data Lane 6.3.5.6.5. Pin Swizzling
7. Intel Agilex® 7 M-Series FPGA EMIF IP – DDR5 Support x
7.1. Intel Agilex 7 M-Series FPGA EMIF IP Parameters for DDR5 7.2. Intel Agilex® 7 M-Series FPGA EMIF IP Pin and Resource Planning 7.3. DDR5 Board Design Guidelines
7.1. Intel Agilex 7 M-Series FPGA EMIF IP Parameters for DDR5 x
7.1.1. Intel Agilex® 7 FPGA EMIF IP Parameter for DDR5 7.1.2. Intel Agilex 7 FPGA EMIF Memory Device Description IP (DDR5) Parameter Descriptions 7.1.3. Intel Agilex 7 FPGA EMIF Calibration IP Parameter Descriptions
7.2. Intel Agilex® 7 M-Series FPGA EMIF IP Pin and Resource Planning x
7.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins 7.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources 7.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP 7.2.4. Pin Placements for Intel Agilex 7 M-Series FPGA DDR5 EMIF IP 7.2.5. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines
7.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins x
7.2.1.1. Estimating Pin Requirements 7.2.1.2. DIMM Options 7.2.1.3. Maximum Number of Interfaces
7.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources x
7.2.2.1. OCT 7.2.2.2. PLL
7.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP x
7.2.3.1. General Guidelines - DDR5 7.2.3.2. x4 DIMM Implementation 7.2.3.3. Specific Pin Connection Requirements 7.2.3.4. Command and Address Signals 7.2.3.5. Clock Signals 7.2.3.6. Data, Data Strobes, DM, and Optional ECC Signals
7.2.4. Pin Placements for Intel Agilex 7 M-Series FPGA DDR5 EMIF IP x
7.2.4.1. Address and Command Pin Placement for DDR5 7.2.4.2. DDR5 Data Width Mapping
7.2.5. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines x
7.2.5.1. DDR5 Byte Lane Swapping 7.2.5.2. DDR5 Address and Command and CLK Lane 7.2.5.3. DDR5 Interface x8 Data Lane 7.2.5.4. DDR5 Interface x4 Data Lane 7.2.5.5. Pin Swizzling
7.3. DDR5 Board Design Guidelines x
7.3.1. PCB Stack-up and Design Considerations 7.3.2. General Design Considerations 7.3.3. DDR Differential Signals Routing 7.3.4. Ground Plane and Return Path 7.3.5. RDIMM, UDIMM, and SODIMM Break-in Layout Guidelines 7.3.6. DRAM Break-in Layout Guidelines 7.3.7. DDR5 PCB Layout Guidelines 7.3.8. DDR5 Simulation Strategy
7.3.7. DDR5 PCB Layout Guidelines x
7.3.7.1. DDR5 Discrete Component/Memory Down Topology: up to 40-Bit Interface (1 Rank x8 or x16, 2 Rank x8 or x16) 7.3.7.2. Routing Guidelines for DDR5 Memory Down: 1 Rank or 2 Rank (x8 bit or x16 bit) Configurations 7.3.7.3. Routing Guidelines for DDR5 RDIMM, UDIMM, and SODIMM Configurations 7.3.7.4. Example of a DDR5 layout on Intel FPGA Platform Board
8. Intel Agilex 7 M-Series FPGA EMIF IP – LPDDR5 Support x
8.1. Intel Agilex 7 M-Series FPGA EMIF IP Parameters for LPDDR5 8.2. Intel Agilex® 7 M-Series FPGA EMIF IP Pin and Resource Planning 8.3. LPDDR5 Board Design Guidelines
8.1. Intel Agilex 7 M-Series FPGA EMIF IP Parameters for LPDDR5 x
8.1.1. Intel Agilex® 7 FPGA EMIF IP Parameter for LPDDR5 8.1.2. Intel Agilex 7 FPGA EMIF Memory Device Description IP (LPDDR5) Parameter Descriptions 8.1.3. Intel Agilex 7 FPGA EMIF Calibration IP Parameter Descriptions
8.2. Intel Agilex® 7 M-Series FPGA EMIF IP Pin and Resource Planning x
8.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins 8.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources 8.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP 8.2.4. Pin Placements for Intel Agilex 7 M-Series FPGA LPDDR5 EMIF IP
8.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins x
8.2.1.1. Estimating Pin Requirements 8.2.1.2. DIMM Options 8.2.1.3. Maximum Number of Interfaces
8.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources x
8.2.2.1. OCT 8.2.2.2. PLL
8.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP x
8.2.3.1. General Guidelines - LPDDR5 8.2.3.2. Specific Pin Connection Requirements 8.2.3.3. Command and Address Signals 8.2.3.4. Clock Signals
8.2.4. Pin Placements for Intel Agilex 7 M-Series FPGA LPDDR5 EMIF IP x
8.2.4.1. Address and Command Pin Placement for LPDDR5 8.2.4.2. LPDDR5 Data Width Mapping 8.2.4.3. LPDDR5 Byte Lane Swapping
8.3. LPDDR5 Board Design Guidelines x
8.3.1. PCB Stack-up and Design Considerations 8.3.2. General Design Considerations 8.3.3. DDR Differential Signals Routing 8.3.4. Ground Plane and Return Path 8.3.5. DRAM Break-in Layout Guidelines 8.3.6. LPDDR5 PCB Layout Guidelines 8.3.7. LPDDR5 Simulation Strategy
8.3.6. LPDDR5 PCB Layout Guidelines x
8.3.6.1. LPDDR5 Discrete Component/Memory Down Topology (1 Rank or 2 Rank, up to 64 Bit Interface) 8.3.6.2. Supported LPDDR5 Topologies 8.3.6.3. Example of an LPDDR5 Layout on an Intel® FPGA Platform Board
9. Intel Agilex® 7 M-Series FPGA EMIF IP – Timing Closure x
9.1. Timing Closure 9.2. Optimizing Timing
9.1. Timing Closure x
9.1.1. Timing Analysis
9.1.1. Timing Analysis x
9.1.1.1. PHY or Core
10. Intel Agilex® 7 M-Series FPGA EMIF IP – Controller Optimization x
10.1. Interface Standard 10.2. Bank Management Efficiency 10.3. Data Transfer 10.4. Improving Controller Efficiency
10.4. Improving Controller Efficiency x
10.4.1. Frequency of Operation 10.4.2. Series of Reads or Writes
11. Intel Agilex® 7 M-Series FPGA EMIF IP – Debugging x
11.1. Interface Configuration Performance Issues 11.2. Functional Issue Evaluation 11.3. Timing Issue Characteristics 11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 11.5. Generating Traffic with the Test Engine IP 11.6. Guidelines for Developing HDL for Traffic Generator 11.7. Debugging with the External Memory Interface Debug Toolkit
11.1. Interface Configuration Performance Issues x
11.1.1. Interface Configuration Bottleneck and Efficiency Issues
11.2. Functional Issue Evaluation x
11.2.1. Intel® IP Memory Model 11.2.2. Vendor Memory Model 11.2.3. Transcript Window Messages
11.3. Timing Issue Characteristics x
11.3.1. Evaluating FPGA Timing Issues 11.3.2. Evaluating External Memory Interface Timing Issues
11.7. Debugging with the External Memory Interface Debug Toolkit x
11.7.1. Prerequisites for Using the EMIF Debug Toolkit 11.7.2. Configuring Your Design to Use the EMIF Debug Toolkit 11.7.3. Launching the EMIF Debug Toolkit 11.7.4. Using the EMIF Debug Toolkit
11.7.4. Using the EMIF Debug Toolkit x
11.7.4.1. Rerunning Calibration 11.7.4.2. Rerunning the Test Engine 11.7.4.3. Saving Debug Print 11.7.4.4. Calibration Reports 11.7.4.5. Driver Margining Tab 11.7.4.6. Pin Delay Settings Tab
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
2. Intel Agilex® 7 M-Series FPGA EMIF IP – Introduction
3. Intel Agilex® 7 M-Series FPGA EMIF IP – Product Architecture
4. Intel Agilex 7 M-Series FPGA EMIF IP – End-User Signals
5. Intel Agilex® 7 M-Series FPGA EMIF IP – Simulating Memory IP
6. Intel Agilex 7 M-Series FPGA EMIF IP – DDR4 Support
7. Intel Agilex® 7 M-Series FPGA EMIF IP – DDR5 Support
8. Intel Agilex 7 M-Series FPGA EMIF IP – LPDDR5 Support
9. Intel Agilex® 7 M-Series FPGA EMIF IP – Timing Closure
10. Intel Agilex® 7 M-Series FPGA EMIF IP – Controller Optimization
11. Intel Agilex® 7 M-Series FPGA EMIF IP – Debugging
12. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

8.1.2. Intel Agilex 7 FPGA EMIF Memory Device Description IP (LPDDR5) Parameter Descriptions

The following topics describe the parameters available on each tab of the IP parameter editor, which you can use to configure your IP. Each parameter with an adjacent checkbox can be auto-computed. The checkbox to the left of the parameter controls whether its value is auto-computed (true) or set manually (false). If there is no checkbox to the left of a parameter, then it must be set manually.
Table 158.  Group: Configuration Save
Display Name Description
Configuration Filepath

Filepath to Save to (.qprs extension)

(Identifier: MEM_CONFIG_FILE_QPRS)
Table 159.  Group: High-Level Parameters
Display Name Description
Memory Format

Specifies the packaging format of the memory device

(Identifier: MEM_FORMAT)
Memory WCK Frequency for this FSP

Specifies the Write Clock Frequency for this Frequency Set Point

Note: This parameter can be auto-computed.

(Identifier: PHY_MEMCLK_FQD_FREQ_MHZ)
Number of Channels in Memory Package

Number of Channels in Memory Package. This value must be consistent with the same MEM_NUM_CHANNELS parameter in the top-level EMIF IP GUI.

(Identifier: LPDDR5_MEM_DEVICE_NUM_CHANNELS)
Number of Ranks Per Channel

Number of Ranks Per Channel in Memory Package. This value must be consistent with the same MEM_NUM_RANKS parameter in the top-level EMIF IP GUI.

(Identifier: LPDDR5_MEM_DEVICE_NUM_RANKS_PER_CHANNEL)
Number of Individual DRAM Components Per Rank

Number of Individual DRAM Components Per Rank in Memory Package. This value must be consistent with the same MEM_COMPS_PER_RANK parameter in the top-level EMIF IP GUI.

(Identifier: LPDDR5_MEM_DEVICE_NUM_COMPS_PER_RANK)
Density of Each Memory Die

Specifies the density of the memory die in Gb

(Identifier: LPDDR5_MEM_DEVICE_DENSITY_GBITS)
Enable Write Data Bus Inversion

Enables Write Data Bus Inversion

(Identifier: LPDDR5_MEM_DEVICE_WR_DBI_EN)
Enable Data Mask

Enables Data Masking for write operations

(Identifier: LPDDR5_MEM_DEVICE_DM_EN)
Table 160.  Group: Memory Interface Parameters / Data Bus
Display Name Description
DQ Width per DRAM Component

Specifies the DQ width of each LPDDR5 DRAM component. As byte mode is not supported, this value is always 16. To form x32 LP5 interfaces, select 2 components per rank at the EMIF IP level.

(Identifier: LPDDR5_MEM_DEVICE_DQ_WIDTH)
Total DQ Width Per Channel

Total DQ Width Per Channel. For LPDDR5 packages, this is the product of the per-DRAM DQ Width and Number of Individual DRAM Components per Rank.

(Identifier: LPDDR5_MEM_DEVICE_TOTAL_DQ_WIDTH_PER_CHANNEL)
Burst Length

Burst Length

(Identifier: LPDDR5_MEM_DEVICE_BURST_LENGTH)
Table 161.  Group: Memory Interface Parameters / Device Topology
Display Name Description
Device Row Address Width

Specifies the row address width of this LPDDR5 DRAM component. This value is auto-derived from the specified component density.

(Identifier: LPDDR5_MEM_DEVICE_ROW_ADDR_WIDTH)
Device Maximum Bank Address Width

Specifies the maximum bank address width. This value is fixed as per the JEDEC standard and cannot be changed.

(Identifier: LPDDR5_MEM_DEVICE_MAX_BA_WIDTH)
Device Maximum Bank Group Address Width

Specifies the maximum bank group address width. This value is fixed as per the JEDEC standard and cannot be changed.

(Identifier: LPDDR5_MEM_DEVICE_MAX_BG_WIDTH)
Device Column Address Width

Specifies the column address width of this LPDDR5 DRAM component. This value is fixed for all component densities as per the JEDEC standard and cannot be changed.

(Identifier: LPDDR5_MEM_DEVICE_COL_ADDR_WIDTH)
Device Burst Address Width

Specifies the burst address width. This value is fixed as per the JEDEC standard and cannot be changed.

(Identifier: LPDDR5_MEM_DEVICE_BURST_ADDR_WIDTH)
Table 162.  Group: Memory Timing Parameters / Timing Parameters
Display Name Description
Memory Speedbin

Maximum Data Rate for which this memory device is rated for

(Identifier: LPDDR5_MEM_DEVICE_SPEEDBIN)
Memory Write Latency Set

Selects the Write Latency Set for this device. Selection affects auto-calculation of Write Latency.

(Identifier: LPDDR5_MEM_DEVICE_WLS)
Memory Read Latency

Read Latency of the memory device for this Frequency Set Point in clock cycles

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_CL_CYC_FQD)
Memory Write Latency

Write Latency of the memory device for this Frequency Set Point in clock cycles

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_CWL_CYC_FQD)
Table 163.  Group: Memory Timing Parameters / Pre- and Post-Amble Options
Display Name Description
Read Postamble Mode

RDQS Postamble Mode for this Frequency Set Point

(Identifier: LPDDR5_MEM_DEVICE_RDQS_PST_MODE_FQD)
Read Preamble Cycles

RDQS Preamble Length

(Identifier: LPDDR5_MEM_DEVICE_RD_PREAMBLE_CYC)
Read Postamble Cycles

RDQS Postamble Length

(Identifier: LPDDR5_MEM_DEVICE_RD_POSTAMBLE_CYC)
Write Postamble Cycles

WCK Postamble Length

(Identifier: LPDDR5_MEM_DEVICE_WR_POSTAMBLE_CYC)
Table 164.  Group: Memory Timing Parameters / Advanced Timing Parameters
Display Name Description
Min Number of Refs Reqd

Minimum Number of Refreshes Required

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_MINNUMREFSREQ)
tRCD

RAS-to-CAS Delay in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRCD_NS)
tRPab

All-Bank Precharge Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRPAB_NS)
tRPpb

Per-Bank Precharge Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRPPB_NS)
tRAS

Row Active Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRAS_NS)
tRAS_Max

Maximum Row Active Time in us

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRAS_MAX_US)
tWR

Write Recovery Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TWR_NS)
tRRD_L

RAS-to-RAS (Active Bank-A to Active Bank-B) Delay Time (Long) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRRD_L_NS)
tRRD_S

RAS-to-RAS (Active Bank-A to Active Bank-B) Delay Time (Short) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRRD_S_NS)
tFAW

Four-bank ACTIVE window time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TFAW_NS)
tRBTP

Read Burst End to Precharge Command Delay in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRBTP_NS)
tWTR_S

Write-to-Read Delay (Short) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TWTR_S_NS)
tWTR_L

Write-to-Read Delay (Long) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TWTR_L_NS)
tPPD

Precharge-to-Precharge Delay Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TPPD_NS)
tRC

Activate-to-Activate command period (same bank) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRC_NS)
tZQLAT

ZQCAL Latch Quiet Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TZQLAT_NS)
tPW_RESET

Min RESET_n low time for Reset Initialization with Stable Power Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TPW_RESET_NS)
tERQE

Enhanced RDQS Toggle Mode Entry Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TERQE_NS)
tERQX

Enhanced RDQS Toggle Mode Exit Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TERQX_NS)
tRDQE_OD

ODT-disable from Enhanced RDQS Toggle Mode Entry Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRDQE_OD_NS)
tRDQX_OD

ODT-enable from Enhanced RDQS Toggle Mode Exit Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRDQX_OD_NS)
tRDQSTFE

Read/Write-based RDQS_t Training Mode Entry Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRDQSTFE_NS)
tRDQSTFX

Read/Write-based RDQS_t Training Mode Exit Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRDQSTFX_NS)
tCCDMW

CAS-to-CAS Delay for Masked Write in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TCCDMW_NS)
tREFW

Refresh Window in ms

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TREFW_MS)
tREFI

Refresh Interval Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TREFI_NS)
tRFCab

All-Bank Refresh Cycle Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRFCAB_NS)
tRFCpb

Per-Bank Refresh Cycle Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRFCPB_NS)
tpbR2pbR

Per-Bank Refresh to Per-Bank Refresh minimum interval time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TPBR2PBR_NS)
tpbR2ACT

Per-Bank Refresh to Activate minimum interval time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TPBR2ACT_NS)
tCKCSH

Valid Clock Requirement before CS goes High (Power-Down AC Timings) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TCKCSH_NS)
tCMDPD

Delay from valid command to Power Down Entry in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TCMDPD_NS)
tXP

Exit Power-Down to next valid command Delay in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TXP_NS)
tCSH

Minimum CS High Pulse Width at Power Down Exit in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TCSH_NS)
tCSLCK

Valid Clock Requirement after Power Down Entry in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TCSLCK_NS)
tCSPD

Delay time from Power Down Entry to CS going High in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TCSPD_NS)
tMRWPD

Delay from MRW Command to Power Down Entry in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TMRWPD_NS)
tZQPD

Delay from ZQ Calibration Start/Latch Command to Power Down Entry in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TZQPD_NS)
tESPD

Delay time from Self-Refresh Entry command to Power Down Entry command in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TESPD_NS)
tSR

Minimum Self-Refresh Time (Entry to Exit) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TSR_NS)
tXSR

Exit Self-Refresh time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TXSR_NS)
tMRR

Mode Register Read Command Period in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TMRR_NS)
tMRW

Mode Register Write Command Period in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TMRW_NS)
tMRD

Mode Register Set Command Delay in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TMRD_NS)
tOSCO

Delay time from Stop WCK2DQI/WCK2DQO Interval Oscillator Command to Mode Register Readout time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TOSCO_NS)
tDQSCK_MAX

Maximum additional delay needed for tDQSCK in Picoseconds

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TDQSCK_MAX_PS)
tDQSCK_MIN

Minimum additional delay needed for tDQSCK in Picoseconds

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TDQSCK_MIN_PS)
Level Two Title