External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

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Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP 2. Intel Agilex® 7 M-Series FPGA EMIF IP – Introduction 3. Intel Agilex® 7 M-Series FPGA EMIF IP – Product Architecture 4. Intel Agilex 7 M-Series FPGA EMIF IP – End-User Signals 5. Intel Agilex® 7 M-Series FPGA EMIF IP – Simulating Memory IP 6. Intel Agilex 7 M-Series FPGA EMIF IP – DDR4 Support 7. Intel Agilex® 7 M-Series FPGA EMIF IP – DDR5 Support 8. Intel Agilex 7 M-Series FPGA EMIF IP – LPDDR5 Support 9. Intel Agilex® 7 M-Series FPGA EMIF IP – Timing Closure 10. Intel Agilex® 7 M-Series FPGA EMIF IP – Controller Optimization 11. Intel Agilex® 7 M-Series FPGA EMIF IP – Debugging 12. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP x
1.1. Release Information
2. Intel Agilex® 7 M-Series FPGA EMIF IP – Introduction x
2.1. Intel Agilex® 7 M-Series EMIF IP Protocol and Feature Support 2.2. Intel Agilex® 7 M-Series EMIF IP Design Flow 2.3. Intel Agilex® 7 M-Series EMIF IP Design Checklist
3. Intel Agilex® 7 M-Series FPGA EMIF IP – Product Architecture x
3.1. Intel Agilex® 7 M-Series EMIF Architecture: Introduction 3.2. Intel Agilex® 7 M-Series EMIF Sequencer 3.3. Intel Agilex® 7 M-Series EMIF Controller 3.4. Intel Agilex® 7 M-Series EMIF IP for Hard Processor Subsystem (HPS)
3.1. Intel Agilex® 7 M-Series EMIF Architecture: Introduction x
3.1.1. Intel Agilex® 7 M-Series EMIF Architecture: I/O Subsystem 3.1.2. Intel Agilex® 7 M-Series EMIF Architecture: I/O SSM 3.1.3. Intel Agilex® 7 M-Series EMIF Architecture: I/O Bank 3.1.4. Intel Agilex® 7 M-Series EMIF Architecture: I/O Lane 3.1.5. Intel Agilex® 7 M-Series EMIF Architecture: Input DQS Clock Tree 3.1.6. Intel Agilex® 7 M-Series EMIF Architecture: PHY Clock Tree 3.1.7. Intel Agilex® 7 M-Series EMIF Architecture: PLL Reference Clock Networks 3.1.8. Intel Agilex® 7 M-Series EMIF Architecture: Clock Phase Alignment 3.1.9. User Clock in Different Core Access Modes
3.1.3. Intel Agilex® 7 M-Series EMIF Architecture: I/O Bank x
3.1.3.1. Lockstep Configuration 3.1.3.2. DDR4 Pin Placement 3.1.3.3. DDR5 Pin Placement 3.1.3.4. LPDDR5 Pin Placement 3.1.3.5. I/O Sub-Bank Usage
3.2. Intel Agilex® 7 M-Series EMIF Sequencer x
3.2.1. Intel Agilex® 7 M-Series Mailbox Structure and Register Definitions
3.2.1. Intel Agilex® 7 M-Series Mailbox Structure and Register Definitions x
3.2.1.1. Mailbox Supported Commands 3.2.1.2. Mailbox Command Definitions
3.3. Intel Agilex® 7 M-Series EMIF Controller x
3.3.1. Hard Memory Controller
3.3.1. Hard Memory Controller x
3.3.1.1. Hard Memory Controller Features
4. Intel Agilex 7 M-Series FPGA EMIF IP – End-User Signals x
4.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interfaces for DDR4 4.2. Intel Agilex® 7 M-Series FPGA EMIF IP Interfaces for DDR5 4.3. Intel Agilex® 7 M-Series FPGA EMIF IP Interfaces for LPDDR5 4.4. Intel Agilex® 7 M-Series FPGA EMIF IP Interfaces for EMIF Calibration Component
4.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interfaces for DDR4 x
4.1.1. ref_clk for EMIF 4.1.2. core_init_n for EMIF 4.1.3. usr_async_clk for EMIF 4.1.4. usr_clk for EMIF 4.1.5. usr_rst_n for EMIF 4.1.6. s0_axi4 for EMIF 4.1.7. mem for EMIF 4.1.8. oct for EMIF
4.2. Intel Agilex® 7 M-Series FPGA EMIF IP Interfaces for DDR5 x
4.2.1. ref_clk for EMIF 4.2.2. core_init_n for EMIF 4.2.3. usr_async_clk for EMIF 4.2.4. usr_clk for EMIF 4.2.5. usr_rst_n for EMIF 4.2.6. s0_axi4 for EMIF 4.2.7. mem for EMIF 4.2.8. i3c for EMIF 4.2.9. mem_lbd for EMIF 4.2.10. mem_lbs for EMIF 4.2.11. oct for EMIF
4.3. Intel Agilex® 7 M-Series FPGA EMIF IP Interfaces for LPDDR5 x
4.3.1. ref_clk for EMIF 4.3.2. core_init_n for EMIF 4.3.3. usr_async_clk for EMIF 4.3.4. usr_clk for EMIF 4.3.5. usr_rst_n for EMIF 4.3.6. s0_axi4 for EMIF 4.3.7. mem for EMIF 4.3.8. oct for EMIF
4.4. Intel Agilex® 7 M-Series FPGA EMIF IP Interfaces for EMIF Calibration Component x
4.4.1. s0_axi4lite_clk for EMIF 4.4.2. s0_axi4lite_rst_n for EMIF 4.4.3. s0_axi4lite for EMIF
5. Intel Agilex® 7 M-Series FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example
6. Intel Agilex 7 M-Series FPGA EMIF IP – DDR4 Support x
6.1. Intel Agilex 7 M-Series FPGA EMIF IP Parameters for DDR4 6.2. Intel Agilex® 7 M-Series FPGA EMIF IP Pin and Resource Planning 6.3. DDR4 Board Design Guidelines
6.1. Intel Agilex 7 M-Series FPGA EMIF IP Parameters for DDR4 x
6.1.1. Intel Agilex® 7 FPGA EMIF IP Parameter for DDR4 6.1.2. Intel Agilex 7 FPGA EMIF Memory Device Description IP (DDR4) Parameter Descriptions 6.1.3. Intel Agilex 7 FPGA EMIF Calibration IP Parameter Descriptions
6.2. Intel Agilex® 7 M-Series FPGA EMIF IP Pin and Resource Planning x
6.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins 6.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources 6.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP 6.2.4. Pin Placements for Intel Agilex® 7 M-Series FPGA DDR4 EMIF IP
6.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins x
6.2.1.1. Estimating Pin Requirements 6.2.1.2. DIMM Options 6.2.1.3. Maximum Number of Interfaces
6.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources x
6.2.2.1. OCT 6.2.2.2. PLL
6.2.4. Pin Placements for Intel Agilex® 7 M-Series FPGA DDR4 EMIF IP x
6.2.4.1. Address and Command Pin Placement for DDR4 6.2.4.2. DDR4 Data Width Mapping 6.2.4.3. General Guidelines - DDR4 6.2.4.4. x4 DIMM Implementation 6.2.4.5. Specific Pin Connection Requirements 6.2.4.6. Command and Address Signals 6.2.4.7. Clock Signals 6.2.4.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3. DDR4 Board Design Guidelines x
6.3.1. Terminations for DDR4 with Intel Agilex® 7 M-Series Devices 6.3.2. General Layout Routing Guidelines 6.3.3. Reference Stackup 6.3.4. Intel Agilex® 7 M-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies 6.3.5. DDR4 Routing Guidelines: Discrete (Component) Topologies
6.3.1. Terminations for DDR4 with Intel Agilex® 7 M-Series Devices x
6.3.1.1. Dynamic On-Chip Termination (OCT) 6.3.1.2. Dynamic On-Die Termination (ODT) in DDR4 6.3.1.3. Choosing Terminations on Intel Agilex® 7 M-Series FPGA Devices 6.3.1.4. On-Chip Termination Recommendations for Intel Agilex® 7 M-Series FPGA Devices
6.3.4. Intel Agilex® 7 M-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies x
6.3.4.1. One DIMM per Channel (1DPC) for UDIMM, RDIMM, and SODIMM DDR4 Topologies 6.3.4.2. Skew Matching Guidelines for DIMM Configurations 6.3.4.3. Power Delivery Recommendations for the Memory / DIMM Side
6.3.5. DDR4 Routing Guidelines: Discrete (Component) Topologies x
6.3.5.1. Single Rank x 8 Discrete (Component) Topology 6.3.5.2. Single Rank x 16 Discrete (Component) Topology 6.3.5.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and Single Rank x 16 Discrete (Component) Topologies 6.3.5.4. Skew Matching Guidelines for DDR4 Discrete Configurations 6.3.5.5. Power Delivery Recommendations for DDR4 Discrete Configurations 6.3.5.6. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines
6.3.5.6. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines x
6.3.5.6.1. DDR4 Byte Lane Swapping 6.3.5.6.2. DDR4 Address and Command and CLK Lane 6.3.5.6.3. DDR4 Interface x8 Data Lane 6.3.5.6.4. DDR4 Interface x4 Data Lane 6.3.5.6.5. Pin Swizzling
7. Intel Agilex® 7 M-Series FPGA EMIF IP – DDR5 Support x
7.1. Intel Agilex 7 M-Series FPGA EMIF IP Parameters for DDR5 7.2. Intel Agilex® 7 M-Series FPGA EMIF IP Pin and Resource Planning 7.3. DDR5 Board Design Guidelines
7.1. Intel Agilex 7 M-Series FPGA EMIF IP Parameters for DDR5 x
7.1.1. Intel Agilex® 7 FPGA EMIF IP Parameter for DDR5 7.1.2. Intel Agilex 7 FPGA EMIF Memory Device Description IP (DDR5) Parameter Descriptions 7.1.3. Intel Agilex 7 FPGA EMIF Calibration IP Parameter Descriptions
7.2. Intel Agilex® 7 M-Series FPGA EMIF IP Pin and Resource Planning x
7.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins 7.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources 7.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP 7.2.4. Pin Placements for Intel Agilex 7 M-Series FPGA DDR5 EMIF IP 7.2.5. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines
7.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins x
7.2.1.1. Estimating Pin Requirements 7.2.1.2. DIMM Options 7.2.1.3. Maximum Number of Interfaces
7.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources x
7.2.2.1. OCT 7.2.2.2. PLL
7.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP x
7.2.3.1. General Guidelines - DDR5 7.2.3.2. x4 DIMM Implementation 7.2.3.3. Specific Pin Connection Requirements 7.2.3.4. Command and Address Signals 7.2.3.5. Clock Signals 7.2.3.6. Data, Data Strobes, DM, and Optional ECC Signals
7.2.4. Pin Placements for Intel Agilex 7 M-Series FPGA DDR5 EMIF IP x
7.2.4.1. Address and Command Pin Placement for DDR5 7.2.4.2. DDR5 Data Width Mapping
7.2.5. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines x
7.2.5.1. DDR5 Byte Lane Swapping 7.2.5.2. DDR5 Address and Command and CLK Lane 7.2.5.3. DDR5 Interface x8 Data Lane 7.2.5.4. DDR5 Interface x4 Data Lane 7.2.5.5. Pin Swizzling
7.3. DDR5 Board Design Guidelines x
7.3.1. PCB Stack-up and Design Considerations 7.3.2. General Design Considerations 7.3.3. DDR Differential Signals Routing 7.3.4. Ground Plane and Return Path 7.3.5. RDIMM, UDIMM, and SODIMM Break-in Layout Guidelines 7.3.6. DRAM Break-in Layout Guidelines 7.3.7. DDR5 PCB Layout Guidelines 7.3.8. DDR5 Simulation Strategy
7.3.7. DDR5 PCB Layout Guidelines x
7.3.7.1. DDR5 Discrete Component/Memory Down Topology: up to 40-Bit Interface (1 Rank x8 or x16, 2 Rank x8 or x16) 7.3.7.2. Routing Guidelines for DDR5 Memory Down: 1 Rank or 2 Rank (x8 bit or x16 bit) Configurations 7.3.7.3. Routing Guidelines for DDR5 RDIMM, UDIMM, and SODIMM Configurations 7.3.7.4. Example of a DDR5 layout on Intel FPGA Platform Board
8. Intel Agilex 7 M-Series FPGA EMIF IP – LPDDR5 Support x
8.1. Intel Agilex 7 M-Series FPGA EMIF IP Parameters for LPDDR5 8.2. Intel Agilex® 7 M-Series FPGA EMIF IP Pin and Resource Planning 8.3. LPDDR5 Board Design Guidelines
8.1. Intel Agilex 7 M-Series FPGA EMIF IP Parameters for LPDDR5 x
8.1.1. Intel Agilex® 7 FPGA EMIF IP Parameter for LPDDR5 8.1.2. Intel Agilex 7 FPGA EMIF Memory Device Description IP (LPDDR5) Parameter Descriptions 8.1.3. Intel Agilex 7 FPGA EMIF Calibration IP Parameter Descriptions
8.2. Intel Agilex® 7 M-Series FPGA EMIF IP Pin and Resource Planning x
8.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins 8.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources 8.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP 8.2.4. Pin Placements for Intel Agilex 7 M-Series FPGA LPDDR5 EMIF IP
8.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins x
8.2.1.1. Estimating Pin Requirements 8.2.1.2. DIMM Options 8.2.1.3. Maximum Number of Interfaces
8.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources x
8.2.2.1. OCT 8.2.2.2. PLL
8.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP x
8.2.3.1. General Guidelines - LPDDR5 8.2.3.2. Specific Pin Connection Requirements 8.2.3.3. Command and Address Signals 8.2.3.4. Clock Signals
8.2.4. Pin Placements for Intel Agilex 7 M-Series FPGA LPDDR5 EMIF IP x
8.2.4.1. Address and Command Pin Placement for LPDDR5 8.2.4.2. LPDDR5 Data Width Mapping 8.2.4.3. LPDDR5 Byte Lane Swapping
8.3. LPDDR5 Board Design Guidelines x
8.3.1. PCB Stack-up and Design Considerations 8.3.2. General Design Considerations 8.3.3. DDR Differential Signals Routing 8.3.4. Ground Plane and Return Path 8.3.5. DRAM Break-in Layout Guidelines 8.3.6. LPDDR5 PCB Layout Guidelines 8.3.7. LPDDR5 Simulation Strategy
8.3.6. LPDDR5 PCB Layout Guidelines x
8.3.6.1. LPDDR5 Discrete Component/Memory Down Topology (1 Rank or 2 Rank, up to 64 Bit Interface) 8.3.6.2. Supported LPDDR5 Topologies 8.3.6.3. Example of an LPDDR5 Layout on an Intel® FPGA Platform Board
9. Intel Agilex® 7 M-Series FPGA EMIF IP – Timing Closure x
9.1. Timing Closure 9.2. Optimizing Timing
9.1. Timing Closure x
9.1.1. Timing Analysis
9.1.1. Timing Analysis x
9.1.1.1. PHY or Core
10. Intel Agilex® 7 M-Series FPGA EMIF IP – Controller Optimization x
10.1. Interface Standard 10.2. Bank Management Efficiency 10.3. Data Transfer 10.4. Improving Controller Efficiency
10.4. Improving Controller Efficiency x
10.4.1. Frequency of Operation 10.4.2. Series of Reads or Writes
11. Intel Agilex® 7 M-Series FPGA EMIF IP – Debugging x
11.1. Interface Configuration Performance Issues 11.2. Functional Issue Evaluation 11.3. Timing Issue Characteristics 11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 11.5. Generating Traffic with the Test Engine IP 11.6. Guidelines for Developing HDL for Traffic Generator 11.7. Debugging with the External Memory Interface Debug Toolkit
11.1. Interface Configuration Performance Issues x
11.1.1. Interface Configuration Bottleneck and Efficiency Issues
11.2. Functional Issue Evaluation x
11.2.1. Intel® IP Memory Model 11.2.2. Vendor Memory Model 11.2.3. Transcript Window Messages
11.3. Timing Issue Characteristics x
11.3.1. Evaluating FPGA Timing Issues 11.3.2. Evaluating External Memory Interface Timing Issues
11.7. Debugging with the External Memory Interface Debug Toolkit x
11.7.1. Prerequisites for Using the EMIF Debug Toolkit 11.7.2. Configuring Your Design to Use the EMIF Debug Toolkit 11.7.3. Launching the EMIF Debug Toolkit 11.7.4. Using the EMIF Debug Toolkit
11.7.4. Using the EMIF Debug Toolkit x
11.7.4.1. Rerunning Calibration 11.7.4.2. Rerunning the Test Engine 11.7.4.3. Saving Debug Print 11.7.4.4. Calibration Reports 11.7.4.5. Driver Margining Tab 11.7.4.6. Pin Delay Settings Tab
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
2. Intel Agilex® 7 M-Series FPGA EMIF IP – Introduction
3. Intel Agilex® 7 M-Series FPGA EMIF IP – Product Architecture
4. Intel Agilex 7 M-Series FPGA EMIF IP – End-User Signals
5. Intel Agilex® 7 M-Series FPGA EMIF IP – Simulating Memory IP
6. Intel Agilex 7 M-Series FPGA EMIF IP – DDR4 Support
7. Intel Agilex® 7 M-Series FPGA EMIF IP – DDR5 Support
8. Intel Agilex 7 M-Series FPGA EMIF IP – LPDDR5 Support
9. Intel Agilex® 7 M-Series FPGA EMIF IP – Timing Closure
10. Intel Agilex® 7 M-Series FPGA EMIF IP – Controller Optimization
11. Intel Agilex® 7 M-Series FPGA EMIF IP – Debugging
12. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

3.1.3.3. DDR5 Pin Placement

Table 10.  DDR5 Pin Placement
Lane Number Pin Index x32+ECC * x 32 2ch x16 x16 + ECC * x16
BL7 95     MEM_1_MEM_DQ[15]    
94     MEM_1_MEM_DQ[14]    
93     MEM_1_MEM_DQ[13]    
92     MEM_1_MEM_DQ[12]    
91          
90     MEM_1_MEM_DM_N[1]    
89     MEM_1_MEM_DQS_C[1]    
88     MEM_1_MEM_DQS_T[1]    
87     MEM_1_MEM_DQ[11]    
86     MEM_1_MEM_DQ[10]    
85     MEM_1_MEM_DQ[9]    
84     MEM_1_MEM_DQ[8]    
BL6 83 MEM_DQ[39]*   MEM_1_MEM_DQ[7]    
82 MEM_DQ[38]*   MEM_1_MEM_DQ[6]    
81 MEM_DQ[37]*   MEM_1_MEM_DQ[5]    
80 MEM_DQ[36]*   MEM_1_MEM_DQ[4]    
79          
78 MEM_DM_N[4]   MEM_1_MEM_DM_N[0]    
77 MEM_DQS_C[4]   MEM_1_MEM_DQS_C[0]    
76 MEM_DQS_T[4]   MEM_1_MEM_DQS_T[0]    
75 MEM_DQ[35]*   MEM_1_MEM_DQ[3]    
74 MEM_DQ[34]*   MEM_1_MEM_DQ[2]    
73 MEM_DQ[33]*   MEM_1_MEM_DQ[1]    
72 MEM_DQ[32]*   MEM_1_MEM_DQ[0]    
BL5 71 MEM_DQ[31] MEM_DQ[31] MEM_1_CK_C[1]    
70 MEM_DQ[30] MEM_DQ[30] MEM_1_CK_T[1]    
69 MEM_DQ[29] MEM_DQ[29] MEM_1_MEM_CS_N[0]    
68 MEM_DQ[28] MEM_DQ[28] MEM_1_MEM_CS_N[1]    
67     MEM_1_CK_C[0]    
66 MEM_DM_N[3] MEM_DM_N[3] MEM_1_CK_T[0]    
65 MEM_DQS_C[3] MEM_DQS_C[3] MEM_1_MEM_CA[12]    
64 MEM_DQS_T[3] MEM_DQS_T[3] MEM_1_MEM_CA[11]    
63 MEM_DQ[27] MEM_DQ[27] MEM_1_RESET_N    
62 MEM_DQ[26] MEM_DQ[26] OCT_1_OCT_RZQIN    
61 MEM_DQ[25] MEM_DQ[25] MEM_1_ALERT_N    
60 MEM_DQ[24] MEM_DQ[24] MEM_1_MEM_CA[10]    
BL4 59 MEM_DQ[23] MEM_DQ[23]

Differential "NSide" Reference Clock Input Site

 MEM_DQ[23]*  
58 MEM_DQ[22] MEM_DQ[22]

Differential "PSide" Reference Clock Input Site

 MEM_DQ[22]*  
57 MEM_DQ[21] MEM_DQ[21] MEM_1_MEM_CA[9] MEM_DQ[21]*  
56 MEM_DQ[20] MEM_DQ[20] MEM_1_MEM_CA[8] MEM_DQ[20]*  
55     MEM_1_MEM_CA[7]    
54 MEM_DM_N[2] MEM_DM_N[2] MEM_1_MEM_CA[6] MEM_DM_N[2]  
53 MEM_DQS_C[2] MEM_DQS_C[2] MEM_1_MEM_CA[5] MEM_DQS_C[2]  
52 MEM_DQS_T[2] MEM_DQS_T[2] MEM_1_MEM_CA[4] MEM_DQS_T[2]  
51 MEM_DQ[19] MEM_DQ[19] MEM_1_MEM_CA[3] MEM_DQ[19]*  
50 MEM_DQ[18] MEM_DQ[18] MEM_1_MEM_CA[2] MEM_DQ[18]*  
49 MEM_DQ[17] MEM_DQ[17] MEM_1_MEM_CA[1] MEM_DQ[17]*  
48 MEM_DQ[16] MEM_DQ[16] MEM_1_MEM_CA[0] MEM_DQ[16]*  
BL3 47 MEM_CK_C[1] MEM_CK_C[1] MEM_0_CK_C[1] MEM_CK_C[1] MEM_CK_C[1]
46 MEM_CK_T[1] MEM_CK_T[1] MEM_0_CK_T[1] MEM_CK_T[1] MEM_CK_T[1]
45 MEM_CS_N[0] MEM_CS_N[0] MEM_0_MEM_CS_N[0] MEM_CS_N[0] MEM_CS_N[0]
44 MEM_CS_N[1] MEM_CS_N[1] MEM_0_MEM_CS_N[1] MEM_CS_N[1] MEM_CS_N[1]
43 MEM_CK_C[0] MEM_CK_C[0] MEM_0_CK_C[0] MEM_CK_C[0] MEM_CK_C[0]
42 MEM_CK_T[0] MEM_CK_T[0] MEM_0_CK_T[0] MEM_CK_T[0] MEM_CK_T[0]
41 MEM_CA[12] MEM_CA[12] MEM_0_MEM_CA[12] MEM_CA[12] MEM_CA[12]
40 MEM_CA[11] MEM_CA[11] MEM_0_MEM_CA[11] MEM_CA[11] MEM_CA[11]
39 MEM_RESET_N[0] MEM_RESET_N[0] MEM_0_RESET_N MEM_RESET_N[0] MEM_RESET_N[0]
38 RZQ Site RZQ Site OCT_0_OCT_RZQIN RZQ Site RZQ Site
37 MEM_ALERT_N[0] MEM_ALERT_N[0] MEM_0_ALERT_N MEM_ALERT_N[0] MEM_ALERT_N[0]
36 MEM_CA[10] MEM_CA[10] MEM_0_MEM_CA[10] MEM_CA[10] MEM_CA[10]
BL2 35 Differential "N-Side" Reference Clock Input Site Differential "N-Side" Reference Clock Input Site

Differential "NSide" Reference Clock Input Site

 Differential "N-Side" Reference Clock Input Site Differential "N-Side" Reference Clock Input Site
34 Differential "P-Side" Reference Clock Input Site Differential "P-Side" Reference Clock Input Site

Differential "PSide" Reference Clock Input Site

 Differential "P-Side" Reference Clock Input Site Differential "P-Side" Reference Clock Input Site
33 MEM_CA[9] MEM_CA[9] MEM_0_MEM_CA[9] MEM_CA[9] MEM_CA[9]
32 MEM_CA[8] MEM_CA[8] MEM_0_MEM_CA[8] MEM_CA[8] MEM_CA[8]
31 MEM_CA[7] MEM_CA[7] MEM_0_MEM_CA[7] MEM_CA[7] MEM_CA[7]
30 MEM_CA[6] MEM_CA[6] MEM_0_MEM_CA[6] MEM_CA[6] MEM_CA[6]
29 MEM_CA[5] MEM_CA[5] MEM_0_MEM_CA[5] MEM_CA[5] MEM_CA[5]
28 MEM_CA[4] MEM_CA[4] MEM_0_MEM_CA[4] MEM_CA[4] MEM_CA[4]
27 MEM_CA[3] MEM_CA[3] MEM_0_MEM_CA[3] MEM_CA[3] MEM_CA[3]
26 MEM_CA[2] MEM_CA[2] MEM_0_MEM_CA[2] MEM_CA[2] MEM_CA[2]
25 MEM_CA[1] MEM_CA[1] MEM_0_MEM_CA[1] MEM_CA[1] MEM_CA[1]
24 MEM_CA[0] MEM_CA[0] MEM_0_MEM_CA[0] MEM_CA[0] MEM_CA[0]
BL1 23 MEM_DQ[7] MEM_DQ[7] MEM_0_MEM_DQ[7] MEM_DQ[7] MEM_DQ[7]
22 MEM_DQ[6] MEM_DQ[6] MEM_0_MEM_DQ[6] MEM_DQ[6] MEM_DQ[6]
21 MEM_DQ[5] MEM_DQ[5] MEM_0_MEM_DQ[5] MEM_DQ[5] MEM_DQ[5]
20 MEM_DQ[4] MEM_DQ[4] MEM_0_MEM_DQ[4] MEM_DQ[4] MEM_DQ[4]
19          
18 MEM_DM_N[0] MEM_DM_N[0] MEM_0_MEM_DM_N[0] MEM_DM_N[0] MEM_DM_N[0]
17 MEM_DQS_C[0] MEM_DQS_C[0] MEM_0_MEM_DQS_C[0] MEM_DQS_C[0] MEM_DQS_C[0]
16 MEM_DQS_T[0] MEM_DQS_T[0] MEM_0_MEM_DQS_T[0] MEM_DQS_T[0] MEM_DQS_T[0]
15 MEM_DQ[3] MEM_DQ[3] MEM_0_MEM_DQ[3] MEM_DQ[3] MEM_DQ[3]
14 MEM_DQ[2] MEM_DQ[2] MEM_0_MEM_DQ[2] MEM_DQ[2] MEM_DQ[2]
13 MEM_DQ[1] MEM_DQ[1] MEM_0_MEM_DQ[1] MEM_DQ[1] MEM_DQ[1]
12 MEM_DQ[0] MEM_DQ[0] MEM_0_MEM_DQ[0] MEM_DQ[0] MEM_DQ[0]
BL0 11 MEM_DQ[15] MEM_DQ[15] MEM_0_MEM_DQ[15] MEM_DQ[15] MEM_DQ[15]
10 MEM_DQ[14] MEM_DQ[14] MEM_0_MEM_DQ[14] MEM_DQ[14] MEM_DQ[14]
9 MEM_DQ[13] MEM_DQ[13] MEM_0_MEM_DQ[13] MEM_DQ[13] MEM_DQ[13]
8 MEM_DQ[12] MEM_DQ[12] MEM_0_MEM_DQ[12] MEM_DQ[12] MEM_DQ[12]
7          
6 MEM_DM_N[1] MEM_DM_N[1] MEM_0_MEM_DM_N[1] MEM_DM_N[1] MEM_DM_N[1]
5 MEM_DQS_C[1] MEM_DQS_C[1] MEM_0_MEM_DQS_C[1] MEM_DQS_C[1] MEM_DQS_C[1]
4 MEM_DQS_T[1] MEM_DQS_T[1] MEM_0_MEM_DQS_T[1] MEM_DQS_T[1] MEM_DQS_T[1]
3 MEM_DQ[11] MEM_DQ[11] MEM_0_MEM_DQ[11] MEM_DQ[11] MEM_DQ[11]
2 MEM_DQ[10] MEM_DQ[10] MEM_0_MEM_DQ[10] MEM_DQ[10] MEM_DQ[10]
1 MEM_DQ[9] MEM_DQ[9] MEM_0_MEM_DQ[9] MEM_DQ[9] MEM_DQ[9]
0 MEM_DQ[8] MEM_DQ[8] MEM_0_MEM_DQ[8] MEM_DQ[8] MEM_DQ[8]
Note: The presence of an asterisk (*) in the above table indicates an ECC byte location.
Level Two Title