External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 12/04/2023
Public

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6.3.1.4. On-Chip Termination Recommendations for Intel Agilex® 7 M-Series FPGA Devices

In the EMIF IP parameter editor you can select values from drop-down lists for each of the following:

  • output mode drive strength for the address/command bus.
  • output mode drive strength for the memory clock.
  • output mode drive strength for the data bus.
  • input mode termination strength for the data bus.

The range of available values may vary, depending on your memory protocol and silicon revision.

You can use the default values as starting points; however, for best results, you should sweep the entire range of legal values and generate multiple hardware designs to determine the optimal settings for your board and memory device.

Once you have found the optimal settings for your design, uncheck the Use Default I/O settings checkbox and use your optimal settings for all future compilations, even if those settings align with the default settings. This ensures that your settings are preserved if the IP is upgraded to a future version.