External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 12/04/2023
Public

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7.2.5.1. DDR5 Byte Lane Swapping

The data lane can be swapped when the byte-lanes are utilized as DQ/DQS pins. Byte lane swapping on utilized lanes is allowed when you swap all the DQ/DQS/DM pins in the same byte lane with the other utilized byte lane.

The rules for swapping DQ byte lane are as follows:

  • You can only swap between utilized DQ lanes.
  • You cannot swap a DQ lane with an AC lane.
  • You cannot swap a DQ lane with an ECC lane when out-of-band ECC is enabled. For x40 interfaces, the highest-indexed DQ byte lane cannot be swapped.
  • Additional restrictions apply when you use a x16 memory component:
    • You must place DQ group 0 and DQ group 1 on adjacent byte lanes, unless they are separated by AC Lanes. These 2 groups must be connected to the same x16 memory component.
    • You must place DQ group 2 and DQ group 3 on adjacent byte lanes, unless they are separated by AC Lanes. These 2 groups must be connected to the same x16 memory component.
    • If you use only one byte of the x16 memory component, you must use only the lower byte of the memory component.
Table 131.  Byte Lane Swapping
Address/Command Scheme Data Width per Channel BL7 [P95:P84] BL6 [P83:P72] BL5 [P71:P60] BL4 [P59:P48] BL3 [P47:P36] BL2 [P35:P24] BL1 [P23:P12] BL0 [P11:P0]
Scheme 1 DDR5 x32 GPIO GPIO DQ[3] P DQ[2] P AC1 P AC0 P DQ[0] P DQ[1] P
Scheme 1 DDR5 x32+ ECC GPIO DQ[ECC] P DQ[3] P DQ[2] P AC1 P AC0 P DQ[0] P DQ[1] P
Note: P = Primary controller.

Example 1: DDR5 x32

BL0, 1, 4, 5 are used as DQ lanes. Byte lane swapping is allowed.

Example 2: DDR5 x32 + ECC

BL6 is used as ECC DQ lane, while BL0, 1, 4, and 5 are used as DQ lanes. Byte lane swapping is allowed on BL0, 1, 4, and 5 only.