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1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
2. Intel Agilex® 7 M-Series FPGA EMIF IP – Introduction
3. Intel Agilex® 7 M-Series FPGA EMIF IP – Product Architecture
4. Intel Agilex 7 M-Series FPGA EMIF IP – End-User Signals
5. Intel Agilex® 7 M-Series FPGA EMIF IP – Simulating Memory IP
6. Intel Agilex 7 M-Series FPGA EMIF IP – DDR4 Support
7. Intel Agilex® 7 M-Series FPGA EMIF IP – DDR5 Support
8. Intel Agilex 7 M-Series FPGA EMIF IP – LPDDR5 Support
9. Intel Agilex® 7 M-Series FPGA EMIF IP – Timing Closure
10. Intel Agilex® 7 M-Series FPGA EMIF IP – Controller Optimization
11. Intel Agilex® 7 M-Series FPGA EMIF IP – Debugging
12. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide
3.1.1. Intel Agilex® 7 M-Series EMIF Architecture: I/O Subsystem
3.1.2. Intel Agilex® 7 M-Series EMIF Architecture: I/O SSM
3.1.3. Intel Agilex® 7 M-Series EMIF Architecture: I/O Bank
3.1.4. Intel Agilex® 7 M-Series EMIF Architecture: I/O Lane
3.1.5. Intel Agilex® 7 M-Series EMIF Architecture: Input DQS Clock Tree
3.1.6. Intel Agilex® 7 M-Series EMIF Architecture: PHY Clock Tree
3.1.7. Intel Agilex® 7 M-Series EMIF Architecture: PLL Reference Clock Networks
3.1.8. Intel Agilex® 7 M-Series EMIF Architecture: Clock Phase Alignment
3.1.9. User Clock in Different Core Access Modes
6.2.4.1. Address and Command Pin Placement for DDR4
6.2.4.2. DDR4 Data Width Mapping
6.2.4.3. General Guidelines - DDR4
6.2.4.4. x4 DIMM Implementation
6.2.4.5. Specific Pin Connection Requirements
6.2.4.6. Command and Address Signals
6.2.4.7. Clock Signals
6.2.4.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3.5.1. Single Rank x 8 Discrete (Component) Topology
6.3.5.2. Single Rank x 16 Discrete (Component) Topology
6.3.5.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and Single Rank x 16 Discrete (Component) Topologies
6.3.5.4. Skew Matching Guidelines for DDR4 Discrete Configurations
6.3.5.5. Power Delivery Recommendations for DDR4 Discrete Configurations
6.3.5.6. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines
7.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins
7.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources
7.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP
7.2.4. Pin Placements for Intel Agilex 7 M-Series FPGA DDR5 EMIF IP
7.2.5. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines
7.3.1. PCB Stack-up and Design Considerations
7.3.2. General Design Considerations
7.3.3. DDR Differential Signals Routing
7.3.4. Ground Plane and Return Path
7.3.5. RDIMM, UDIMM, and SODIMM Break-in Layout Guidelines
7.3.6. DRAM Break-in Layout Guidelines
7.3.7. DDR5 PCB Layout Guidelines
7.3.8. DDR5 Simulation Strategy
7.3.7.1. DDR5 Discrete Component/Memory Down Topology: up to 40-Bit Interface (1 Rank x8 or x16, 2 Rank x8 or x16)
7.3.7.2. Routing Guidelines for DDR5 Memory Down: 1 Rank or 2 Rank (x8 bit or x16 bit) Configurations
7.3.7.3. Routing Guidelines for DDR5 RDIMM, UDIMM, and SODIMM Configurations
7.3.7.4. Example of a DDR5 layout on Intel FPGA Platform Board
11.1. Interface Configuration Performance Issues
11.2. Functional Issue Evaluation
11.3. Timing Issue Characteristics
11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer
11.5. Generating Traffic with the Test Engine IP
11.6. Guidelines for Developing HDL for Traffic Generator
11.7. Debugging with the External Memory Interface Debug Toolkit
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7.2.5.1. DDR5 Byte Lane Swapping
The data lane can be swapped when the byte-lanes are utilized as DQ/DQS pins. Byte lane swapping on utilized lanes is allowed when you swap all the DQ/DQS/DM pins in the same byte lane with the other utilized byte lane.
The rules for swapping DQ byte lane are as follows:
- You can only swap between utilized DQ lanes.
- You cannot swap a DQ lane with an AC lane.
- You cannot swap a DQ lane with an ECC lane when out-of-band ECC is enabled. For x40 interfaces, the highest-indexed DQ byte lane cannot be swapped.
- Additional restrictions apply when you use a x16 memory component:
- You must place DQ group 0 and DQ group 1 on adjacent byte lanes, unless they are separated by AC Lanes. These 2 groups must be connected to the same x16 memory component.
- You must place DQ group 2 and DQ group 3 on adjacent byte lanes, unless they are separated by AC Lanes. These 2 groups must be connected to the same x16 memory component.
- If you use only one byte of the x16 memory component, you must use only the lower byte of the memory component.
Address/Command Scheme | Data Width per Channel | BL7 [P95:P84] | BL6 [P83:P72] | BL5 [P71:P60] | BL4 [P59:P48] | BL3 [P47:P36] | BL2 [P35:P24] | BL1 [P23:P12] | BL0 [P11:P0] |
---|---|---|---|---|---|---|---|---|---|
Scheme 1 | DDR5 x32 | GPIO | GPIO | DQ[3] P | DQ[2] P | AC1 P | AC0 P | DQ[0] P | DQ[1] P |
Scheme 1 | DDR5 x32+ ECC | GPIO | DQ[ECC] P | DQ[3] P | DQ[2] P | AC1 P | AC0 P | DQ[0] P | DQ[1] P |
Note: P = Primary controller.
|
Example 1: DDR5 x32
BL0, 1, 4, 5 are used as DQ lanes. Byte lane swapping is allowed.
Example 2: DDR5 x32 + ECC
BL6 is used as ECC DQ lane, while BL0, 1, 4, and 5 are used as DQ lanes. Byte lane swapping is allowed on BL0, 1, 4, and 5 only.