Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 2/15/2023
Public
Document Table of Contents

5.8.2.3. RSDS, Mini-LVDS, and PPDS I/O Standard in Intel® Cyclone® 10 LP Devices

The RSDS, mini-LVDS, and PPDS I/O standards are used in chip-to-chip applications between the timing controller and the column drivers on the display panels such as LCD monitor panels and LCD televisions.

To support RSDS, mini-LVDS, and PPDS output standards, Intel® Cyclone® 10 LP devices conform to the following specifications:

  • National Semiconductor Corporation RSDS Interface Specification
  • Texas Instruments mini-LVDS Interface Specification
  • National Semiconductor Corporation PPDS Interface Specification

Intel® Cyclone® 10 LP I/O banks support RSDS, mini-LVDS, and PPDS output standards:

  • The right I/O banks support true RSDS, mini-LVDS, and PPDS transmitters.
  • The top and bottom I/O banks support emulated RSDS, mini-LVDS, and PPDS transmitters with external resistors.
Figure 75. RSDS, Mini-LVDS, or PPDS Interface with True Output Buffer on the Right Side I/O Banks


Figure 76. Emulated RSDS, Mini-LVDS, or PPDS Interface with External Resistor Network on the Top and Bottom I/O Banks


A resistor network is required to attenuate the output voltage swing to meet RSDS, mini-LVDS, and PPDS specifications when using emulated transmitters. You can modify the resistor network values to reduce power or improve the noise margin.

Equation 1. Resistor Network ValuesThe resistor values must satisfy this equation.

Note: Intel recommends that you perform simulations using Intel® Cyclone® 10 LP devices IBIS models to validate the custom resistor values meet the RSDS, mini-LVDS, or PPDS requirements.

For an RSDS interface, you can use a single external resistor instead of three. The single-resistor solution reduces the external resistor count while still achieving the required RSDS signaling level. However, the performance is lower than with a three-resistor network.

Figure 77. RSDS Interface with Single Resistor Network on the Top and Bottom I/O Banks