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1. Logic Elements and Logic Array Blocks in Intel® Cyclone® 10 LP Devices
2. Embedded Memory Blocks in Intel® Cyclone® 10 LP Devices
3. Embedded Multipliers in Intel® Cyclone® 10 LP Devices
4. Clock Networks and PLLs in Intel® Cyclone® 10 LP Devices
5. I/O and High Speed I/O in Intel® Cyclone® 10 LP Devices
6. Configuration and Remote System Upgrades
7. SEU Mitigation in Intel® Cyclone® 10 LP Devices
8. JTAG Boundary-Scan Testing for Intel® Cyclone® 10 LP Devices
9. Power Management in Intel® Cyclone® 10 LP Devices
2.1. Embedded Memory Capacity
2.2. Intel® Cyclone® 10 LP Embedded Memory General Features
2.3. Intel® Cyclone® 10 LP Embedded Memory Operation Modes
2.4. Intel® Cyclone® 10 LP Embedded Memory Clock Modes
2.5. Intel® Cyclone® 10 LP Embedded Memory Configurations
2.6. Intel® Cyclone® 10 LP Embedded Memory Design Consideration
2.7. Embedded Memory Blocks in Intel® Cyclone® 10 LP Devices Revision History
4.2.1. PLL Features
4.2.2. PLL Architecture
4.2.3. External Clock Outputs
4.2.4. Clock Feedback Modes
4.2.5. Clock Multiplication and Division
4.2.6. Post-Scale Counter Cascading
4.2.7. Programmable Duty Cycle
4.2.8. PLL Control Signals
4.2.9. Clock Switchover
4.2.10. Programmable Bandwidth
4.2.11. Programmable Phase Shift
4.2.12. PLL Cascading
4.2.13. PLL Reconfiguration
4.2.14. Spread-Spectrum Clocking
5.1. Intel® Cyclone® 10 LP I/O Standards Support
5.2. I/O Resources in Intel® Cyclone® 10 LP Devices
5.3. Intel FPGA I/O IP Cores for Intel® Cyclone® 10 LP Devices
5.4. Intel® Cyclone® 10 LP I/O Elements
5.5. Intel® Cyclone® 10 LP Clock Pins Input Support
5.6. Programmable IOE Features in Intel® Cyclone® 10 LP Devices
5.7. I/O Standards Termination
5.8. Intel® Cyclone® 10 LP High-Speed Differential I/Os and SERDES
5.9. Using the I/Os and High Speed I/Os in Intel® Cyclone® 10 LP Devices
5.10. I/O and High Speed I/O in Intel® Cyclone® 10 LP Devices Revision History
5.8.2.1. LVDS I/O Standard in Intel® Cyclone® 10 LP Devices
5.8.2.2. Bus LVDS I/O Standard in Intel® Cyclone® 10 LP Devices
5.8.2.3. RSDS, Mini-LVDS, and PPDS I/O Standard in Intel® Cyclone® 10 LP Devices
5.8.2.4. LVPECL I/O Standard in Intel® Cyclone® 10 LP Devices
5.8.2.5. Differential SSTL I/O Standard in Intel® Cyclone® 10 LP Devices
5.8.2.6. Differential HSTL I/O Standard in Intel® Cyclone® 10 LP Devices
5.9.1. Guideline: Validate Your Pin Placement
5.9.2. Guideline: Check for Illegal Pad Placements
5.9.3. Guideline: Voltage-Referenced I/O Standards Restriction
5.9.4. Guideline: Simultaneous Usage of Multiple I/O Standards
5.9.5. Guideline: LVTTL or LVCMOS Inputs in Intel® Cyclone® 10 LP Devices
5.9.6. Guideline: Differential Pad Placement
5.9.7. Guideline: Board Design for Signal Quality
6.1.4.1. Configuring Intel® Cyclone® 10 LP Devices with the JRunner Software Driver
6.1.4.2. Configuring Intel® Cyclone® 10 LP Devices with Jam STAPL
6.1.4.3. JTAG Single-Device Configuration
6.1.4.4. JTAG Multi-Device Configuration
6.1.4.5. Combining JTAG and AS Configuration Schemes
6.1.4.6. Programming Serial Configuration Devices In-System with the JTAG Interface
6.1.4.7. JTAG Instructions
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5.8. Intel® Cyclone® 10 LP High-Speed Differential I/Os and SERDES
The Intel® Cyclone® 10 LP devices use registers and logic in the core fabric to implement LVDS input and output interfaces.
- For LVDS transmitters, Intel® Cyclone® 10 LP devices use the double data rate I/O (DDIO) registers that reside in the I/O elements (IOE). For LVDS receivers, the devices use the DDIO registers in the core fabric. This architecture improves performance with regards to the receiver input skew margin (RSKM) or transmitter channel-to-channel skew (TCCS).
- For the LVDS serializer/deserializer (SERDES), Intel® Cyclone® 10 LP devices use logic elements (LE) registers.
- The device uses shift registers, internal phase-locked loops (PLLs), and I/O cells to perform serial-to-parallel conversions on incoming data and parallel-to-serial conversion on outgoing data.
Note: In Intel® Cyclone® 10 LP devices, the interface configured using the ALTLVDS IP core always sends the MSB of your parallel data first.
Section Content
High-Speed Differential I/O Interface
Differential I/O Standards Support
High-Speed I/O Timing Budget
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