Visible to Intel only — GUID: sss1396493843003
Ixiasoft
Visible to Intel only — GUID: sss1396493843003
Ixiasoft
1.2.2. LAB Control Signals
The control signals include:
- Two clock signals
- Two clock enable signals
- Two asynchronous clear signals
- One synchronous clear signal
- One synchronous load signal
Control Signal | Description |
---|---|
labclk1 |
|
labclk2 | |
labclkena1 |
|
labclkena2 | |
labclr1 | Asynchronous clear signals:
|
labclr2 | |
syncload | Synchronous load and synchronous clear signals:
|
synclr |
You can use up to eight control signals at a time. Register packing and synchronous load cannot be used simultaneously.
Each LAB can have up to four non-global control signals. You can use additional LAB control signals as long as they are global signals.
An LAB-wide asynchronous load signal to control the logic for the preset signal of the register is not available. The register preset is achieved with a NOT gate push-back technique. Intel® Cyclone® 10 LP devices only support either a preset or asynchronous clear signal.
In addition to the clear port, Intel® Cyclone® 10 LP devices provide a chip-wide reset pin (DEV_CLRn) to reset all registers in the device. An option set before compilation in the Intel® Quartus® Prime software controls this pin. This chip-wide reset overrides all other control signals.