Visible to Intel only — GUID: pdx1489990864868
Ixiasoft
Visible to Intel only — GUID: pdx1489990864868
Ixiasoft
4.1.4. GCLK Network Clock Source Generation
The inputs to the five clock control blocks on each side of the Intel® Cyclone® 10 LP device must be chosen from among the following clock sources:
- Three or four clock input pins, depending on the specific device
- Five PLL counter outputs
- Two DPCLK pins and two CDPCLK pins from both the left and right sides and four DPCLK pins from both the top and bottom
- Five signals from internal logic
From the clock sources listed above, only two clock input pins, two PLL clock outputs, one DPCLK or CDPCLK pin, and one source from internal logic can drive into any given clock control block.
Out of these six inputs to any clock control block, the two clock input pins and two PLL outputs are dynamically selected to feed a GCLK. The clock control block supports static selection of the signal from internal logic.