Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 2/15/2023
Public
Document Table of Contents

6.1.4.6. Programming Serial Configuration Devices In-System with the JTAG Interface

Intel® Cyclone® 10 LP devices in a single- or multiple-device chain support in-system programming of a serial configuration device with the JTAG interface through the SFL design.

The intelligent host or download cable of the board can use the four JTAG pins on the Intel® Cyclone® 10 LP device to program the serial configuration device in system, even if the host or download cable cannot access the configuration pins (DCLK, DATA, ASDI, and nCS).

The SFL design is a JTAG-based in-system programming solution for Intel serial configuration devices. The SFL is a bridge design for the Intel® Cyclone® 10 LP device that uses its JTAG interface to access the JTAG Indirect Configuration Device Programming (.jic) file and then uses the AS interface to program the serial configuration device. In a multiple device chain, you must only configure the master device that controls the serial configuration device. Slave devices in the multiple device chain that are configured by the serial configuration device do not have to be configured when using this feature. To successfully use this feature, set the MSEL pins of the master device to select the AS configuration scheme.

The serial configuration device in-system programming through the Intel® Cyclone® 10 LP device JTAG interface has three stages:
  • Loading the SFL design
  • Configuring the device
  • Reconfiguring the device