Visible to Intel only — GUID: mjo1484226073670
Ixiasoft
Visible to Intel only — GUID: mjo1484226073670
Ixiasoft
6.1.2.3. Passive Serial Single-Device Configuration Using a Download Cable
To configure Intel® Cyclone® 10 LP device, connect the device to a download cable.
- The configuration begins when the external host transfers data from a storage device to the Intel® Cyclone® 10 LP through the download cable.
- The programming hardware or download cable then places the configuration data one bit at a time on the DATA[0] pin of the device.
- The configuration data clocks into the target device until CONF_DONE goes high.
Note: The CONF_DONE pin must have an external 10-kΩ pull-up resistor for the device to initialize.
When you use the Intel FPGA download cable, setting the Auto-restart configuration after error option does not affect the configuration cycle because you must manually restart configuration in the Intel® Quartus® Prime software if an error occurs. The Enable user-supplied start-up clock (CLKUSR) option has no effect on device initialization, because this option is disabled in the .sof when programming the device with the Intel® Quartus® Prime Programmer and download cable. If you turn on the Enable user-supplied start-up clock (CLKUSR) option, you do not have to provide a clock on CLKUSR when you configure the device with the Intel® Quartus® Prime Programmer and a download cable.
- nCONFIG
- nSTATUS
- DCLK
- DATA[0]
- CONF_DONE
All devices in the chain utilize and enter user mode at the same time because all the CONF_DONE pins are tied together. The entire chain halts configuration if any device detects an error because the nSTATUS pins are tied together.