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Ixiasoft
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Ixiasoft
3.1. Embedded Multiplier Block Overview
For multiplications greater than 18 x 18, the Intel® Quartus® Prime software cascades the multiplier blocks to form wider or deeper logic structures. There are no restrictions on the data width of the multiplier but the greater the data width, the slower the multiplication process.
You can control the operation of the embedded multiplier blocks using the following options:
- Parameterize the relevant IP cores with the Quartus Prime parameter editor
- Infer the multipliers directly with VHDL or Verilog HDL
Additionally, you can implement soft multipliers by using the M9K memory blocks as look-up tables (LUTs). The LUTs contain partial results from the multiplication of input data with coefficients that implements variable depth and width high-performance soft multipliers. Using soft multipliers increases the number of available multipliers in the device.