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1. Logic Elements and Logic Array Blocks in Intel® Cyclone® 10 LP Devices
2. Embedded Memory Blocks in Intel® Cyclone® 10 LP Devices
3. Embedded Multipliers in Intel® Cyclone® 10 LP Devices
4. Clock Networks and PLLs in Intel® Cyclone® 10 LP Devices
5. I/O and High Speed I/O in Intel® Cyclone® 10 LP Devices
6. Configuration and Remote System Upgrades
7. SEU Mitigation in Intel® Cyclone® 10 LP Devices
8. JTAG Boundary-Scan Testing for Intel® Cyclone® 10 LP Devices
9. Power Management in Intel® Cyclone® 10 LP Devices
2.1. Embedded Memory Capacity
2.2. Intel® Cyclone® 10 LP Embedded Memory General Features
2.3. Intel® Cyclone® 10 LP Embedded Memory Operation Modes
2.4. Intel® Cyclone® 10 LP Embedded Memory Clock Modes
2.5. Intel® Cyclone® 10 LP Embedded Memory Configurations
2.6. Intel® Cyclone® 10 LP Embedded Memory Design Consideration
2.7. Embedded Memory Blocks in Intel® Cyclone® 10 LP Devices Revision History
4.2.1. PLL Features
4.2.2. PLL Architecture
4.2.3. External Clock Outputs
4.2.4. Clock Feedback Modes
4.2.5. Clock Multiplication and Division
4.2.6. Post-Scale Counter Cascading
4.2.7. Programmable Duty Cycle
4.2.8. PLL Control Signals
4.2.9. Clock Switchover
4.2.10. Programmable Bandwidth
4.2.11. Programmable Phase Shift
4.2.12. PLL Cascading
4.2.13. PLL Reconfiguration
4.2.14. Spread-Spectrum Clocking
5.1. Intel® Cyclone® 10 LP I/O Standards Support
5.2. I/O Resources in Intel® Cyclone® 10 LP Devices
5.3. Intel FPGA I/O IP Cores for Intel® Cyclone® 10 LP Devices
5.4. Intel® Cyclone® 10 LP I/O Elements
5.5. Intel® Cyclone® 10 LP Clock Pins Input Support
5.6. Programmable IOE Features in Intel® Cyclone® 10 LP Devices
5.7. I/O Standards Termination
5.8. Intel® Cyclone® 10 LP High-Speed Differential I/Os and SERDES
5.9. Using the I/Os and High Speed I/Os in Intel® Cyclone® 10 LP Devices
5.10. I/O and High Speed I/O in Intel® Cyclone® 10 LP Devices Revision History
5.8.2.1. LVDS I/O Standard in Intel® Cyclone® 10 LP Devices
5.8.2.2. Bus LVDS I/O Standard in Intel® Cyclone® 10 LP Devices
5.8.2.3. RSDS, Mini-LVDS, and PPDS I/O Standard in Intel® Cyclone® 10 LP Devices
5.8.2.4. LVPECL I/O Standard in Intel® Cyclone® 10 LP Devices
5.8.2.5. Differential SSTL I/O Standard in Intel® Cyclone® 10 LP Devices
5.8.2.6. Differential HSTL I/O Standard in Intel® Cyclone® 10 LP Devices
5.9.1. Guideline: Validate Your Pin Placement
5.9.2. Guideline: Check for Illegal Pad Placements
5.9.3. Guideline: Voltage-Referenced I/O Standards Restriction
5.9.4. Guideline: Simultaneous Usage of Multiple I/O Standards
5.9.5. Guideline: LVTTL or LVCMOS Inputs in Intel® Cyclone® 10 LP Devices
5.9.6. Guideline: Differential Pad Placement
5.9.7. Guideline: Board Design for Signal Quality
6.1.4.1. Configuring Intel® Cyclone® 10 LP Devices with the JRunner Software Driver
6.1.4.2. Configuring Intel® Cyclone® 10 LP Devices with Jam STAPL
6.1.4.3. JTAG Single-Device Configuration
6.1.4.4. JTAG Multi-Device Configuration
6.1.4.5. Combining JTAG and AS Configuration Schemes
6.1.4.6. Programming Serial Configuration Devices In-System with the JTAG Interface
6.1.4.7. JTAG Instructions
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5.2.4. Intel® Cyclone® 10 LP LVDS Channels Support
The LVDS channels available vary among Intel® Cyclone® 10 LP device packages.
Product Line | Package | LVDS Pairs | Device Side | LVDS Pairs Per Side |
---|---|---|---|---|
10CL006 | U256 | 65 | Top | 20 |
Right | 12 | |||
Left | 11 | |||
Bottom | 22 | |||
E144 | 22 | Top | 6 | |
Right | 6 | |||
Left | 3 | |||
Bottom | 7 | |||
10CL010 | M164 | 26 | Top | 9 |
Right | 7 | |||
Left | 3 | |||
Bottom | 7 | |||
U256 | 65 | Top | 20 | |
Right | 12 | |||
Left | 11 | |||
Bottom | 22 | |||
E144 | 22 | Top | 6 | |
Right | 6 | |||
Left | 3 | |||
Bottom | 7 | |||
10CL016 | M164 | 22 | Top | 7 |
Right | 6 | |||
Left | 3 | |||
Bottom | 6 | |||
U256 | 53 | Top | 14 | |
Right | 12 | |||
Left | 9 | |||
Bottom | 18 | |||
U484 | 137 | Top | 36 | |
Right | 37 | |||
Left | 31 | |||
Bottom | 33 | |||
E144 | 19 | Top | 6 | |
Right | 5 | |||
Left | 2 | |||
Bottom | 6 | |||
F484 | 137 | Top | 36 | |
Right | 37 | |||
Left | 31 | |||
Bottom | 33 | |||
10CL025 | U256 | 52 | Top | 17 |
Right | 10 | |||
Left | 10 | |||
Bottom | 15 | |||
E144 | 18 | Top | 5 | |
Right | 5 | |||
Left | 3 | |||
Bottom | 5 | |||
10CL040 | U484 | 124 | Top | 33 |
Right | 32 | |||
Left | 29 | |||
Bottom | 30 | |||
F484 | 124 | Top | 33 | |
Right | 32 | |||
Left | 29 | |||
Bottom | 30 | |||
10CL055 | U484 | 132 | Top | 36 |
Right | 34 | |||
Left | 29 | |||
Bottom | 33 | |||
F484 | 132 | Top | 36 | |
Right | 34 | |||
Left | 29 | |||
Bottom | 33 | |||
10CL080 | U484 | 110 | Top | 29 |
Right | 29 | |||
Left | 26 | |||
Bottom | 26 | |||
F484 | 110 | Top | 29 | |
Right | 29 | |||
Left | 26 | |||
Bottom | 26 | |||
F780 | 178 | Top | 51 | |
Right | 43 | |||
Left | 35 | |||
Bottom | 49 | |||
10CL120 | F484 | 103 | Top | 28 |
Right | 26 | |||
Left | 25 | |||
Bottom | 24 | |||
F780 | 230 | Top | 65 | |
Right | 53 | |||
Left | 49 | |||
Bottom | 63 |