Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 2/15/2023
Public
Document Table of Contents

6.2.1. Power-On Reset (POR) Circuit

The POR circuit keeps the device in reset state until the power supply voltage levels have stabilized during device power up.

After device power up, the device does not release nSTATUS until VCCINT, VCCA, and VCCIO (for I/O banks in which the configuration and JTAG pins reside) are above the POR trip point of the device.
  • VCCINT and VCCA are monitored for brown-out conditions after device power up.
  • VCCA is the analog power to the phase-locked loop (PLL).

In some applications, it is necessary for a device to wake up very quickly to begin operation. Intel® Cyclone® 10 LP devices offer the fast POR time option to support fast wake-up time applications. The fast POR time option has stricter power-up requirements compared to the standard POR time option. You can select either the fast or standard POR option with the MSEL pin settings.

Note: If your system exceeds the fast or standard POR time, you must hold nCONFIG low until all the power supplies are stable.