Visible to Intel only — GUID: nby1488541417901
Ixiasoft
1. Logic Elements and Logic Array Blocks in Intel® Cyclone® 10 LP Devices
2. Embedded Memory Blocks in Intel® Cyclone® 10 LP Devices
3. Embedded Multipliers in Intel® Cyclone® 10 LP Devices
4. Clock Networks and PLLs in Intel® Cyclone® 10 LP Devices
5. I/O and High Speed I/O in Intel® Cyclone® 10 LP Devices
6. Configuration and Remote System Upgrades
7. SEU Mitigation in Intel® Cyclone® 10 LP Devices
8. JTAG Boundary-Scan Testing for Intel® Cyclone® 10 LP Devices
9. Power Management in Intel® Cyclone® 10 LP Devices
2.1. Embedded Memory Capacity
2.2. Intel® Cyclone® 10 LP Embedded Memory General Features
2.3. Intel® Cyclone® 10 LP Embedded Memory Operation Modes
2.4. Intel® Cyclone® 10 LP Embedded Memory Clock Modes
2.5. Intel® Cyclone® 10 LP Embedded Memory Configurations
2.6. Intel® Cyclone® 10 LP Embedded Memory Design Consideration
2.7. Embedded Memory Blocks in Intel® Cyclone® 10 LP Devices Revision History
4.2.1. PLL Features
4.2.2. PLL Architecture
4.2.3. External Clock Outputs
4.2.4. Clock Feedback Modes
4.2.5. Clock Multiplication and Division
4.2.6. Post-Scale Counter Cascading
4.2.7. Programmable Duty Cycle
4.2.8. PLL Control Signals
4.2.9. Clock Switchover
4.2.10. Programmable Bandwidth
4.2.11. Programmable Phase Shift
4.2.12. PLL Cascading
4.2.13. PLL Reconfiguration
4.2.14. Spread-Spectrum Clocking
5.1. Intel® Cyclone® 10 LP I/O Standards Support
5.2. I/O Resources in Intel® Cyclone® 10 LP Devices
5.3. Intel FPGA I/O IP Cores for Intel® Cyclone® 10 LP Devices
5.4. Intel® Cyclone® 10 LP I/O Elements
5.5. Intel® Cyclone® 10 LP Clock Pins Input Support
5.6. Programmable IOE Features in Intel® Cyclone® 10 LP Devices
5.7. I/O Standards Termination
5.8. Intel® Cyclone® 10 LP High-Speed Differential I/Os and SERDES
5.9. Using the I/Os and High Speed I/Os in Intel® Cyclone® 10 LP Devices
5.10. I/O and High Speed I/O in Intel® Cyclone® 10 LP Devices Revision History
5.8.2.1. LVDS I/O Standard in Intel® Cyclone® 10 LP Devices
5.8.2.2. Bus LVDS I/O Standard in Intel® Cyclone® 10 LP Devices
5.8.2.3. RSDS, Mini-LVDS, and PPDS I/O Standard in Intel® Cyclone® 10 LP Devices
5.8.2.4. LVPECL I/O Standard in Intel® Cyclone® 10 LP Devices
5.8.2.5. Differential SSTL I/O Standard in Intel® Cyclone® 10 LP Devices
5.8.2.6. Differential HSTL I/O Standard in Intel® Cyclone® 10 LP Devices
5.9.1. Guideline: Validate Your Pin Placement
5.9.2. Guideline: Check for Illegal Pad Placements
5.9.3. Guideline: Voltage-Referenced I/O Standards Restriction
5.9.4. Guideline: Simultaneous Usage of Multiple I/O Standards
5.9.5. Guideline: LVTTL or LVCMOS Inputs in Intel® Cyclone® 10 LP Devices
5.9.6. Guideline: Differential Pad Placement
5.9.7. Guideline: Board Design for Signal Quality
6.1.4.1. Configuring Intel® Cyclone® 10 LP Devices with the JRunner Software Driver
6.1.4.2. Configuring Intel® Cyclone® 10 LP Devices with Jam STAPL
6.1.4.3. JTAG Single-Device Configuration
6.1.4.4. JTAG Multi-Device Configuration
6.1.4.5. Combining JTAG and AS Configuration Schemes
6.1.4.6. Programming Serial Configuration Devices In-System with the JTAG Interface
6.1.4.7. JTAG Instructions
Visible to Intel only — GUID: nby1488541417901
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5.1. Intel® Cyclone® 10 LP I/O Standards Support
Intel® Cyclone® 10 LP devices support a wide range of I/O standards, including single-ended, voltage-referenced single-ended, and differential I/O standards.
I/O Standard | Type | I/O Bank | Direction | Application | Standard Support | |
---|---|---|---|---|---|---|
Input | Output | |||||
3.3 V LVTTL/3.3 V LVCMOS 15 | Single-ended | All | Yes | Yes | General purpose | JESD8-B |
3.0 V LVTTL/3.0 V LVCMOS15 | Single-ended | All | Yes | Yes | General purpose | JESD8-B |
2.5 V LVTTL/2.5 V LVCMOS | Single-ended | All | Yes | Yes | General purpose | JESD8-5 |
1.8 V LVTTL/1.8 V LVCMOS | Single-ended | All | Yes | Yes | General purpose | JESD8-7 |
1.5 V LVCMOS | Single-ended | All | Yes | Yes | General purpose | JESD8-11 |
1.2 V LVCMOS | Single-ended | All | Yes | Yes | General purpose | JESD8-12 |
3.0 V PCI/3.0 V PCI-X | Single-ended | All | Yes | Yes | General purpose | PCI Rev. 2.2 |
SSTL-2 Class I and II 16 | Voltage-referenced | All | Yes | Yes | General purpose | JESD8-9B |
SSTL-18 Class I and II 16 | Voltage-referenced | All | Yes | Yes | General purpose | JESD8-15 |
1.8 V HSTL Class I and II 16 | Voltage-referenced | All | Yes | Yes | General purpose | JESD8-6 |
1.5 V HSTL Class I and II 16 | Voltage-referenced | All | Yes | Yes | General purpose | JESD8-6 |
1.2 V HSTL Class I | Voltage-referenced | All | Yes | Yes | General purpose | JESD8-16A |
1.2 V HSTL Class II | Voltage-referenced | 1, 2, 5, 6 | Yes | — | ||
3, 4, 7, 8 | Yes | Yes | ||||
Differential SSTL-2 Class I and II 16 | Differential | All | Yes 17 | Yes 18 | General purpose | JESD8-9B |
Differential SSTL-18 Class I 16 | Differential | All | Yes17 | Yes18 | General purpose | JESD8-15 |
Differential SSTL-18 Class II 16 | Differential | All | Yes17 | — | ||
Differential 1.8 V HSTL Class I 16 | Differential | All | Yes17 | Yes18 | General purpose | JESD8-6 |
Differential 1.8 V HSTL Class II 16 | Differential | All | Yes17 | — | ||
Differential 1.5 V HSTL Class I 16 | Differential | All | Yes17 | Yes18 | General purpose | JESD8-6 |
Differential 1.5 V HSTL Class II 16 | Differential | All | Yes17 | — | ||
Differential 1.2 V HSTL Class I | Differential | All | Yes17 | Yes18 | General purpose | JESD8-16A |
Differential 1.2 V HSTL Class II | Differential | All | Yes17 | — | ||
LVDS (dedicated) | Differential | 1, 2, 5, 6 | Yes | Yes | — | ANSI/TIA/EIA-644 |
LVDS (emulated) 19 | Differential | 3, 4, 5, 6, 7, 8 | Yes | Yes | — | ANSI/TIA/EIA-644 |
Mini-LVDS (dedicated) | Differential | 1, 2, 5, 6 | — | Yes | — | — |
Mini-LVDS (emulated)19 | Differential | 3, 4, 5, 6, 7, 8 | — | Yes | — | — |
RSDS (dedicated) | Differential | 1, 2, 5, 6 | — | Yes | — | — |
RSDS (emulated)19 | Differential | 3, 4, 5, 6, 7, 8 | — | Yes | — | — |
PPDS (dedicated) | Differential | 1, 2, 5, 6 | — | Yes | — | — |
PPDS (emulated)19 | Differential | All | — | Yes | — | — |
Differential LVPECL | Differential | All | Yes | — | — | — |
Bus LVDS | Differential | All | Yes20 | Yes18 | — | — |
15 You must enable the PCI clamp diode.
16 Even though the Intel® Cyclone® 10 LP I/O buffers support various I/O standards for memory application, Intel does not validate nor support any IP that is intended for memory applications such as DDR or DDR2.
17 The inputs treat differential inputs as two single-ended inputs but decode only one of them.
18 The outputs uses two single-ended outputs with the second output programmed as inverted.
19 Emulated LVDS, mini-LVDS, RSDS, and PPDS I/O standards requires external resistors.
20 The inputs use LVDS input buffers.