Visible to Intel only — GUID: hco1416492013209
Ixiasoft
Visible to Intel only — GUID: hco1416492013209
Ixiasoft
10.7.2.1.1. Write Timing Margin
Use sources and probes to dynamically control the PLL phase offset control, to increase and decrease the write clock phase adjustment so that the write window size may be ascertained.
Remember that when sweeping PLL clock phases, the following two factors may cause operational failure:
- The available write margin.
- The PLL phase in a multi-clock system.
The following code achieves this adjustment. You should use sources and probes to modify the respective output of the PLL. Ensure that the example driver is writing and reading from the memory while observing the pnf_per_byte signals to see when write failures occur:
///////////////// wire [7:0] Probe_sig; wire [5:0] Source_sig; PhaseCount PhaseCounter ( .resetn (1'b1), .clock (pll_ref_clk), .step (Source_sig[5]), .updown (Source_sig[4]), .offset (Probe_sig) ); CheckoutPandS freq_PandS ( .probe (Probe_sig), .source (Source_sig) ); ddr2_dimm_phy_alt_mem_phy_pll_siii pll ( .inclk0 (pll_ref_clk), .areset (pll_reset), .c0 (phy_clk_1x), // hR .c1 (mem_clk_2x), // FR .c2 (aux_clk), // FR .c3 (write_clk_2x), // FR .c4 (resync_clk_2x), // FR .c5 (measure_clk_1x), // hR .c6 (ac_clk_1x), // hR .phasecounterselect (Source_sig[3:0]), .phasestep (Source_sig[5]), .phaseupdown (Source_sig[4]), .scanclk (scan_clk), .locked (pll_locked_src), .phasedone (pll_phase_done) );