Visible to Intel only — GUID: hco1416491997449
Ixiasoft
Visible to Intel only — GUID: hco1416491997449
Ixiasoft
10.7.1.2.1. Skew
Trace length variations cause data valid window variations between the signals, reducing margin. For example, DDR3-800 at 400 MHz has a data valid window that is smaller than 1,250 ps. Trace length skew or crosstalk can reduce this data valid window further, making it difficult to design a reliably operating memory interface. Ensure that the skew figure previously entered into the Intel® FPGA IP matches that actually achieved on the PCB, otherwise Intel® Quartus® Prime timing analysis of the interface is accurate.