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Ixiasoft
6.2. Signal Terminations
The following table summarizes the extent of OCT support for each device.
Termination Scheme |
HSTL-15 and HSTL-18 |
FPGA Device | |||||
---|---|---|---|---|---|---|---|
Arria II GX |
Arria II GZ, Stratix III, and Stratix IV |
Arria V and Stratix V |
|||||
Column I/O |
Row I/O |
Column I/O |
Row I/O |
Column I/O |
Row I/O |
||
On-Chip Series Termination without Calibration |
Class I |
50 |
50 |
50 |
50 |
— |
— |
On-Chip Series Termination with Calibration |
Class I |
50 |
50 |
50 |
50 |
— |
— |
On-Chip Parallel Termination with Calibration |
Class I |
— |
— |
50 |
50 |
50 |
50 |
Note to Table:
|
On-chip series (RS) termination is supported only on output and bidirectional buffers, while on-chip parallel (RT) termination is supported only on input and bidirectional buffers. Because QDR II SRAM interfaces have unidirectional data paths, dynamic OCT is not required.
For Arria II GX, Stratix III and Stratix IV devices, the HSTL Class I I/O calibrated terminations are calibrated against 50-ohm 1% resistors connected to the RUP and RDN pins in an I/O bank with the same VCCIO as the QDRII SRAM interface. The calibration occurs at the end of the device configuration.
QDR II SRAM controllers have a ZQ pin which is connected via a resistor RQ to ground. Typically the QDR II SRAM output signal impedance is 0.2 × RQ. Refer to the QDR II SRAM device data sheet for more information.
For information about OCT, refer to the I/O Features in Arria II GX Devices chapter in the Arria II GX Device Handbook, I/O Features in Arria V Devices chapter in the Arria V Device Handbook, Stratix III Device I/O Features chapter in the Stratix III Device Handbook, I/O Features in Stratix IV Devices chapter in the Stratix IV Device Handbook , and the I/O Features in Stratix V Devices chapter in the Stratix V Device Handbook .