Visible to Intel only — GUID: hco1416491309703
Ixiasoft
Visible to Intel only — GUID: hco1416491309703
Ixiasoft
5.2. RLDRAM 3 Configurations
The following figure shows the main signal connections between the FPGA and a single CIO RLDRAM 3 component.
Notes to Figure:
- Use external differential termination on CK/CK#.
- Use FPGA parallel on-chip termination (OCT) for terminating QK/QK# and DQ on reads.
- Use RLDRAM 3 component on-die termination (ODT) for terminating DQ, DM, and DK, DK# on writes.
- Use external discrete termination with fly-by placement to avoid stubs.
- Use external discrete termination for this signal, as shown for REF.
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Use external discrete termination, as shown for REF, but you may require a pull-up resistor to VDD as an alternative option. Refer to the RLDRAM 3 device data sheet for more information about RLDRAM 3 power-up sequencing.
The following figure shows the main signal connections between the FPGA and two CIO RLDRAM 3 components in a width expansion configuration.
Notes to Figure:
- Use FPGA parallel OCT for terminating QK/QK# and DQ on reads.
- Use RLDRAM 3 component ODT for terminating DQ, DM, and DK on writes.
- Use external dual 200 Ω differential termination.
- Use external discrete termination at the trace split of the balanced T or Y topology.
- Use external discrete termination at the trace split of the balanced T or Y topology, but you may require a pull-up resistor to VDD as an alternative option. Refer to the RLDRAM 3 device data sheet for more information about RLDRAM 3 power-up sequencing.