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1.1.16.5. Maximum Number of RLDRAM II Interfaces Supported per FPGA
One common I/O ×36 interface consists of:
- 36 DQ
- 1 DM pin
- 2 DK, DK# pin pairs
- 2 QK, QK# pin pairs
- 1 CK, CK# pin pair
- 24 address pins
- 1 CS# pin
- 1 REF# pin
- 1 WE# pin
One common I/O ×9 interface consists of:
- 9 DQ
- 1 DM pins
- 1 DK, DK# pin pair
- 1 QK, QK# pin pair
- 1 CK, CK# pin pair
- 25 address pins
- 1 CS# pin
- 1 REF# pin
- 1 WE# pin
Device |
Device Type |
Package Pin Count |
Maximum Number of RLDRAM II CIO Interfaces |
---|---|---|---|
Arria II GZ |
EP2AGZ300 EP2AGZ350 EP2AGZ225 |
1,517 |
Two ×36 interfaces on each side |
EP2AGZ300 EP2AGZ350 |
780 |
|
|
Arria V |
5AGXB1 5AGXB3 5AGXB5 5AGXB7 5AGTD3 5AGTD7 |
1,517 |
|
5AGXA1 5AGXA3 |
672 |
|
|
5AGXA5 5AGXA7 |
672 |
|
|
Arria V GZ |
5ZGZE5 5ZGZE7 |
1,517 |
|
5AGZE1 5AGZE3 |
780 |
|
|
Stratix III |
EP3SL340 |
1,760 |
|
EP3SE50 EP3SL50 EP3SL70 |
484 |
One ×9 interface on both right and left sides |
|
Stratix IV |
EP4SGX290 EP4SGX360 EP4SGX530 |
1,932 |
|
EP4SE530 EP4SE820 |
1,760 |
|
|
EP4SGX70 EP4SGX110 EP4SGX180 EP4SGX230 |
780 |
One ×36 interface on each side (no DQ pins on right side) |
|
Stratix V |
5SGXA5 5SGXA7 |
1,932 |
|
5SGXA3 5SGXA4 |
780 |
|
Refer also to the EMIF Device Selector, which is available from the Device Selection option of the External Memory Interfaces IP - Support Center page on the Intel® website.